Datasheet

ADV7320/ADV7321
Rev. A | Page 24 of 88
SDATA
SCLOCK
START ADRR R/W ACK SUBADDRESS ACK DATA ACK STOP
1–7 8
9
S
1–7
1–7
P
05067-022
8
9
8
9
Figure 46. Bus Data Transfer
WRITE
SEQUENCE
READ
SEQUENCE
S SLAVE ADDR A(S) SUBADDR A(S) DATA DATA A(S) P
S SLAVE ADDR A(S) SUBADDR A(S) S SLAVE ADDR A(S) DATA DATAA(M) A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A (S) = NO ACKNOWLEDGE BY SLAVE
A (M) = NO ACKNOWLEDGE BY MASTER
LSB = 0
LSB = 1
05067-023
A(S)
Figure 47. Read and Write Sequences