Datasheet

ADV7320/ADV7321
Rev. A | Page 14 of 88
t
9
t
11
CLKIN_A
C9–C0
t
10
t
12
Cb0 Cr0 Cb2 Cr2
CONTROL
INPUTS
t
14
CONTROL
OUTPUTS
t
13
*SELECTED BY ADDRESS 0x01, BIT 7: SEE TABLE 21.
IN MASTER/SLAVE MODE
IN SLAVE MODE
S9–S0/Y9–Y0* Y0 Y2 Y3Y1
S_HSYNC,
S_VSYNC,
S_BLANK
05067-014
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
Figure 14. 16-/20-Bit SD Only Pixel Input Mode (Input Mode 000)
Y0 Y1
Y2 Y3
b
a
Cb1Cr1Cr0Cb0
c
Y
OUTPUT
P_HSYNC
P_VSYNC
P_BLANK
Y9–Y0
C9–C0
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE TIMING SPECIFICATION
SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
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Figure 15. HD 4:2:2 Input Timing Diagram