Datasheet

ADV7320/ADV7321
Rev. A | Page 13 of 88
t
9
t
11
t
10
t
12
t
11
t
12
CLKIN_B
Y9–Y0
CONTROL
INPUTS
Yxxx
Crxxx
Y1
Cr0
Y0
Cb0
P_HSYNC,
P_VSYNC,
P_BLANK
PS INPUT
t
9
t
10
t
11
t
12
SD INPUT
S9–S0
CONTROL
INPUTS
CLKIN_A
Y2
Cb1
Y1Cr0
Y0
Cb0
S_HSYNC,
S_VSYNC,
S_BLANK
05067-012
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
Figure 12. PS 10-Bit and SD 10-Bit Simultaneous Input Mode (Input Mode 100)
t
9
t
11
CLKIN_A
t 10
t
12
CONTROL
INPUTS
t
14
CONTROL
OUTPUTS
t
13
S_HSYNC,
S_VSYNC,
S_BLANK
Y2
Cb1
Y1Cr0
Y0
Cb0
05067-013
S9–S0/Y9–Y0*
*SELECTED BY ADDRESS 0x01, BIT 7: SEE TABLE 21.
IN MASTER/SLAVE MODE
IN SLAVE MODE
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
Figure 13. 8-/10-Bit SD Only Pixel Input Mode (Input Mode 000)