Datasheet

ADV7320/ADV7321
Rev. A | Page 12 of 88
t
9
t
11
t
10
t
12
Y0 Y1
Y2
Y3 Y4 Y5
t
9
t
10
t
11
t
12
HD INPUT
SD INPUT
S9–S0
CONTROL
INPUTS
CLKIN_A
CLKIN_B
Y9–Y0
CONTROL
INPUTS
C9–C0
P_HSYNC,
P_VSYNC,
P_BLANK
Y2
Cb1
Y1
Cr0
Y0
Cb0
S_HSYNC,
S_VSYNC,
S_BLANK
Cr4
Cb4Cr2Cb2
Cr0
Cb0
05067-010
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
Figure 10. HD 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 101: SD Oversampled) (Input Mode 110: HD Oversampled)
t
9
t
11
t
10
t
12
Y0 Y1
Y2
Y3 Y4 Y5
t
9
t
10
t
11
t
12
PS INPUT
SD INPUT
S9–S0
CONTROL
INPUTS
CLKIN_A
CLKIN_B
Y9–Y0
CONTROL
INPUTS
C9–C0
P_HSYNC,
P_VSYNC,
P_BLANK
Y2
Cb1
Y1Cr0
Y0
Cb0
S_HSYNC,
S_VSYNC,
S_BLANK
Cr4
Cb4Cr2Cb2
Cr0
Cb0
05067-011
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
Figure 11. PS 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 011)