Datasheet

ADV7320/ADV7321
Rev. A | Page 11 of 88
t
9
t
11
t
10
t
12
t
14
t
13
CLKIN_A
Y9–Y0
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
CONTROL
INPUTS
CONTROL
OUTPUTS
Yxxx
Crxxx
Y1
Cr0
Y0
Cb0
P_VSYNC,
P_HSYNC,
P_BLANK
05067-007
Figure 7. PS 4:2:2 10-Bit Interleaved at 54 MHz
HSYNC
/
VSYNC
Input Mode (Input Mode 111)
t
9
t
11
t
10
t 12
t
11
t
12
t
13
t
14
CLKIN_B*
*CLKIN_B USED IN THIS PS ONLY MODE.
Y9–Y0
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
CONTROL
OUTPUTS
Y1
Cr0
Y0Cb0XY00003FF
05067-008
Figure 8. PS Only 4:2:2 10-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100)
t
9
t
11
t
10
t
12
t
14
t
13
CLKIN_A
Y9–Y0
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
CONTROL
OUTPUTS
NOTES
1. Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT 1.
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
05067-009
Figure 9. PS Only 4:2:2 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 111)