Datasheet

ADV7320/ADV7321
Rev. A | Page 10 of 88
t
9
t
11
CLKIN_A
C9–C0
t
10
t
12
P_HSYNC,
P_VSYNC,
P_BLANK
CONTROL
INPUTS
G0 G1 G2 G3 G4 G5
B0 B1 B2 B3 B4 B5
R0 R1 R2 R3 R4 R5
Y9–Y0
t
14
CONTROL
OUTPUTS
t
13
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
S9–S0
05067-005
Figure 5. HD RGB 4:4:4 Input Mode (Input Mode 010)
t 9
t
11
t
10
t
12
t
11
t
12
t
13
t
14
CLKIN_B*
*CLKIN_B MUST BE USED IN THIS PS MODE.
Y9–Y0
t
9
= CLOCK HIGH TIME
t
10
= CLOCK LOW TIME
t
11
= DATA SETUP TIME
t
12
= DATA HOLD TIME
t
13
= HD OUTPUT ACCESS TIME
t
14
= HD OUTPUT HOLD TIME
CONTROL
INPUTS
CONTROL
OUTPUTS
Yxxx
Crxxx
Y1
Cr0
Y0
Cb0
P_HSYNC,
P_VSYNC,
P_BLANK
05067-006
Figure 6. PS 4:2:2 10-Bit Interleaved at 27 MHz
HSYNC
/
VSYNC
Input Mode (Input Mode 100)