Datasheet
ADV7194
–9–
REV. A
ABSOLUTE MAXIMUM RATINGS
1
V
AA
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . . . . GND – 0.5 V to V
AA
+ 0.5 V
Storage Temperature (T
S
) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . . . 150°C
Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220°C
Analog Outputs to GND
2
. . . . . . . . . . . . . . GND – 0.5 to V
AA
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
PACKAGE THERMAL PERFORMANCE
The 80-lead package is used for this device. The junction-to-
ambient (θ
JA
) thermal resistance in still air on a four-layer PCB
is 24.7°C.
To reduce power consumption when using this part the user
can run the part on a 3.3 V supply, turn off any unused DACs.
The user must at all times stay below the maximum junction
temperature of 110°C. The following equation shows how to
calculate this junction temperature:
Junction Temperature = (V
AA
× (I
DAC
+ I
CCT
)) × θ
JA
+ 70°C (T
AMB
)
I
DAC
= 10 mA + (sum of the average currents consumed by
each powered-on DAC)
Average current consumed by each powered-on DAC =
(V
REF
× K )/R
SET
V
REF
= 1.235 V
K = 4.2146
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADV7194KST 0°C to 70°C 80-Lead Quad Flatpack ST-80
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7194 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
P2
P3
P4
P5
P6
P7
P8
P9
P0
P1
Y[0]/P10
V
REF
COMP 1
DAC A
DAC B
V
AA
AGND
DAC C
DAC D
AGND
V
AA
DAC E
DAC F
COMP 2
R
SET2
DGND
RESET
PAL_NTSC
R
SET1
ALSB
SCRESET/RTC/TR
DGND
HSYNC
VSYNC
BLANK
TTXREQ
DGND
V
DD
AGND
V
AA
SCL
SDA
CLKIN
CLKOUT
V
DD
Cb[4]
Cb[5]
Cb[6]
Cb[7]
Cb[8]
Cb[9]
80 79 78 77 76 71 70 69 68 67 66 6575 74 73 72 64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17
18
20
19
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DGND
V
DD
Cb[3]
DGND
VSO/ TTX/CLAMP
CSO_HSO
Cb[2]
Cb[1]
Cb[0]
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
V
DD
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
ADV7194
LQFP
Y[1]/P11
Y[2]/P12
Y[3]/P13
Y[4]/P14
Y[5]/P15
Y[6]/P16
Y[7]/P17
Y[8]/P18
Y[9]/P19