Datasheet

ADV7194
–8–
REV. A
t
3
t
2
t
6
t
1
t
7
t
5
t
3
t
4
t
8
SDA
SCL
Figure 1. MPU Port Timing Diagram
t
9
t
11
CLOCK
PIXEL INPUT
DATA
t
10
t
12
HSYNC,
VSYNC,
BLANK
Cb Y Cr Y Cb Y
HSYNC,
VSYNC,
BLANK,
CSO_HSO,
VSO, CLAMP
t
13
t
14
CONTROL
I/PS
CONTROL
O/PS
Figure 2. Pixel and Control Data Timing Diagram
t
16
t
17
t
18
TTXREQ
CLOCK
TTX
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
3 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 3. Teletext Timing Diagram
t
9
t
10
t
12
Y0 Y1 Y2
Y3 Y4
Y5
Cb0 Cb1 Cb2 Cb3 Cb4 Cb5
Cr0 Cr1 Cr2 Cr3 Cr4 Cr5
t
11
CLOCK
Y0 – Y9
INCLUDING
SYNC INFORMATION
Cb0 – Cb9
Cr0 – Cr9
PROGRESSIVE
SCAN INPUT
Figure 4. Progressive Scan Input Timing