Datasheet

ADV7194
–33–
REV. A
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
Mode Register 5 is an 8-bit-wide register. Figure 60 shows
the various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)
This bit controls the component Y output level on the ADV7194.
If this bit is set (0), the encoder outputs Betacam levels when
configured in PAL or NTSC mode. If this bit is set (1), the
encoder outputs SMPTE levels when configured in PAL or
NTSC mode.
UV-Level Control (MR51–MR52)
These bits control the component U and V output levels on
the ADV7194. It is possible to have UV levels with a peak-to-
peak amplitude of either 700 mV (MR52 + MR51 = 01) or
1000 mV (MR52 + MR51 = 10) in NTSC and PAL. It is also
possible to have default values of 934 mV for NTSC and 700 mV
for PAL (MR52 + MR51 = 00).
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay (MR54–MR55)
These bits control the delay or advance of the CLAMP signal in
the front or back porch of the ADV7194. It is possible to delay or
advance the pulse by zero, one, two, or three clock cycles.
Note: TTX functionality is shared with VSO and CLAMP on Pin
62. CLAMP/VSO Select (MR77) and TTX Input/CLAMP/VSO
Output (MR76) have to be set accordingly.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP sig-
nal. If this bit is set (1), the delay is negative. If it is set (0), the
delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is
set (1), the CLAMP signal is located in the back porch position.
If this bit is set (0), the CLAMP signal is located in the front
porch position.
MR57 MR56 MR55 MR54 MR53 MR52 MR51 MR50
0 POSITIVE
1 NEGATIVE
MR56
CLAMP DELAY
DIRECTION
UV-LEVEL CONTROL
MR52 MR51
0 0 DEFAULT LEVELS
0 1 700mV
1 0 1000mV
1 1 RESERVED
0 DISABLE
1 ENABLE
MR53
RGB SYNC
CLAMP
POSITION
0 FRONT PORCH
1 BACK PORCH
MR57
0 DISABLE
1 ENABLE
MR50
Y-LEVEL
CONTROL
CLAMP DELAY
MR55 MR54
0 0 NO DELAY
011  PCLK
102  PCLK
113  PCLK
Figure 60. Mode Register 5, MR5
MR47 MR46 MR45 MR44 MR43 MR42 MR41 MR40
0 DISABLE
1 ENABLE
MR46
COLOR BAR
CONTROL
CHROMINANCE
CONTROL
0 ENABLE COLOR
1 DISABLE COLOR
MR44
GENLOCK CONTROL
MR42 MR41
0 0 DISABLE GENLOCK
0 1 ENABLE SUBCARRIER
RESET PIN
1 0 TIMING RESET
1 1 ENABLE RTC PIN
0 DISABLE
1 ENABLE
MR40
VSYNC 3H
CONTROL
BURST
CONTROL
0 ENABLE BURST
1 DISABLE BURST
MR45
ACTIVE VIDEO
LINE DURATION
0 720 PIXELS
1 710 PIXELS /702 PIXELS
MR43
INTERLACED
MODE CONTROL
0 INTERLACED
1 NONINTERLACED
MR47
Figure 59. Mode Register 4, MR4