Datasheet

ADV7189B
Rev. B | Page 88 of 104
Bits
Subaddress Register Bit Description
7 6 5 4 3 2 1 0 Comments Notes
PVEND[4:0]. How many lines after
l
COUNT
rollover to set V low.
1 0 1 0 0 PAL default (BT.656)
0 Set to low when manual
programming
PVENDSIGN
1 Not suitable for user
programming
0 No delay PVENDDELE. Delay V bit going
low by one line relative to PVEND
(even field).
1 Additional delay by
1 line
0 No delay
0xE9 PAL V Bit
End
PVENDDELO. Delay V bit going
low by one line relative to PVEND
(odd field).
1 Additional delay by
1 line
PFTOG[4:0]. How many lines after
l
COUNT
rollover to toggle F signal.
0 0 0 1 1 PAL default (BT.656)
0 Set to low when manual
programming
PFTOGSIGN
1 Not suitable for user
programming
0xEA PAL F Bit
Toggle
0 No delay
PFTOGDELE. Delay F transition by
one line relative to PFTOG (even
field).
1 Additional delay by
1 line
0 No delay
PFTOGDELO. Delay F transition
by one line relative to PFTOG
(odd field).
1 Additional delay by
1 line
0 0 Low drive strength (1x)
0 1 Medium-low drive
strength (2x)
1 0 Medium-high drive
strength (3x)
DR_STR_S[1:0]. Select the drive
strength for the sync output
signals.
1 1 High drive strength (4x)
0 0 Low drive strength (1x)
0 1 Medium-low drive
strength (2x)
1 0 Medium-high drive
strength (3x)
DR_STR_C[1:0]. Select the drive
strength for the clock output
signal.
1 1 High drive strength (4x)
0 0 Low drive strength (1x)
0 1 Medium-low drive
strength (2x)
1 0 Medium-high drive
strength (3x)
DR_STR[1:0]. Select the drive
strength for the data output
signals. Can be increased or
decreased for EMC or crosstalk
reasons.
1 1 High drive strength (4x)
0xF4 Drive
Strength
Reserved x x No delay
0 0 0 Bypass mode 0dB
2 MHz 5 MHz
0 0 1 −3 dB −2 dB
0 1 0 −6 dB +3.5 dB
0 1 1 −10 dB +5 dB
NTSC filters
100 Reserved
3 MHz 6 MHz
1 0 1 −2 dB +2 dB
1 1 0 −5 dB +3 dB
IFFILTSEL[2:0] IF filter selection
for PAL and NTSC
1 1 1 −7 dB +5 dB
PAL filters
0xF8 IF Comp
Control
Reserved
0 0 0 0 0