Datasheet

ADV7189B
Rev. B | Page 87 of 104
Bits
Subaddress Register Bit Description
7 6 5 4 3 2 1 0 Comments Notes
NVBEG[4:0]. How many lines after
l
COUNT
rollover to set V high.
0 0 1 0 1 NTSC default (BT.656)
0 Set to low when manual
programming
NVBEGSIGN
1 Not suitable for user
programming
0 No delay NVBEGDELE. Delay V bit going
high by one line relative to
NVBEG (even field).
1 Additional delay by
1 line
0 No delay
0xE5 NTSC V Bit
Begin
NVBEGDELO. Delay V bit going
high by one line relative to
NVBEG (odd field).
1 Additional delay by
1 line
NVEND[4:0]. How many lines
after l
COUNT
rollover to set V low.
0 0 1 0 0 NTSC default (BT.656)
0 Set to low when manual
programming
NVENDSIGN
1 Not suitable for user
programming
0 No delay NVENDDELE. Delay V bit going
low by one line relative to NVEND
(even field).
1 Additional delay by
1 line
0 No delay
0xE6 NTSC V Bit
End
NVENDDELO. Delay V bit going
low by one line relative to NVEND
(odd field).
1 Additional delay by
1 line
NFTOG[4:0]. How many lines after
l
COUNT
rollover to toggle F signal.
0 0 0 1 1 NTSC default
0 Set to low when manual
programming
NFTOGSIGN
1 Not suitable for user
programming
0 No delay NFTOGDELE. Delay F transition
by one line relative to NFTOG
(even field).
1 Additional delay by
1 line
0 No delay
0xE7 NTSC F Bit
Toggle
NFTOGDELO. Delay F transition
by one line relative to NFTOG
(odd field).
1 Additional delay by
1 line
PVBEG[4:0]. How many lines after
l
COUNT
rollover to set V high.
0 0 1 0 1 PAL default (BT.656)
0 Set to low when manual
programming
PVBEGSIGN
1 Not suitable for user
programming
0 No delay PVBEGDELE. Delay V bit going
high by one line relative to
PVBEG (even field).
1 Additional delay by
1 line
0 No delay
0xE8 PAL V Bit
Begin
PVBEGDELO. Delay V bit going
high by one line relative to
PVBEG (odd field).
1 Additional delay by
1 line