Datasheet

ADV7189B
Rev. B | Page 80 of 104
Bits
Subaddress Register Bit Description
7 6 5 4 3 2 1 0 Comments Notes
HSE[10:8]. HS end allows the
positioning of the HS output within
the video line.
0 0 0 HS output ends HSE[10:0]
pixels after the falling
edge of Hsync
Reserved 0 Set to 0
HSB[10:8]. HS begin allows the
positioning of the HS output within
the video line.
0 0 0 HS output starts HSB[10:0]
pixels after the falling
edge of Hsync
0x34 HS Position
Control 1
Reserved
0 Set to 0
0x35 HS Position
Control 2
HSB[7:0] See above, using
HSB[10:0] and HSE[10:0], the user
can program the position and
length of HS output signal.
0 0 0 0 0 0 1 0
0x36 HS Position
Control 3
HSE[7:0] See above. 0 0 0 0 0 0 0 0
Using HSB and HSE
the user can program
the position and
length of the output
Hsync
0 Invert polarity PCLK. Sets the polarity of LLC1.
1 Normal polarity as per
timing diagrams
Reserved 0 0 Set to 0
0 Active high PF. Sets the FIELD polarity.
1 Active low
Reserved 0 Set to 0
0 Active high PVS. Sets the VS polarity.
1 Active low
Reserved 0 Set to 0
0 Active high
0x37 Polarity
PHS. Sets HS polarity.
1 Active low