Datasheet

ADV7189B
Rev. B | Page 70 of 104
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0 Masks CCAPD_Q bit CCAPD_MSKB
1 Unmasks CCAPD_Q bit
0 Masks GEMD_Q bit GEMD_MSKB
1 Unmasks GEMD_Q bit
0 Masks CGMS_CHNGD_Q bit CGMS_CHNGD_MSKB
1 Unmasks CGMS_CHNGD_Q bit
0 Masks WSS_CHNGD_Q bit WSS_CHNGD_MSKB
1 Unmasks WSS_CHNGD_Q bit
Reserved 0 Not used
Reserved 0 Not used
Reserved 0 Not used
0 Masks MPU_STIM_INTRQ_Q bit
0x48 Interrupt
Mask 2
Read/
Write
Register
Access
Page 2
MPU_STIM_INTRQ_MSKB
1 Unmasks MPU_STIM_INTRQ_Q
bit
0 SD 60 Hz signal output SD_OP_50Hz
SD 60/50Hz frame rate at
output
1 SD 50 Hz signal output
0 SD vertical sync lock not
established
SD_V_LOCK
1 SD vertical sync lock
established
0 SD horizontal sync lock not
established
SD_H_LOCK
1 SD horizontal sync lock
established
Reserved x Not used
0 SECAM lock not established SCM_LOCK
SECAM Lock
1 SECAM lock established
Reserved x Not used
Reserved x Not used
0x49 Raw Status
3
Read Only
Register
Register
Access
Page 2
Reserved x Not used
These bits
cannot be
cleared or
masked.
Register
0x4A is used
for this
purpose.
0 No change in SD signal standard
detected at the input
SD_OP_CHNG_Q
SD 60/50 Hz frame rate at
input
1 A change in SD signal standard
is detected at the input
0 No change in SD vertical sync
lock status
SD_V_LOCK_CHNG_Q
1 SD vertical sync lock status has
changed.
0 No change in SD horizontal sync
lock status
SD_H_LOCK_CHNG_Q
1 SD horizontal sync lock status
has changed
x No change in AD_RESULT[2:0]
bits in Status Register 1
SD_AD_CHNG_Q
SD autodetect changed
AD_RESULT[2:0] bits in Status
Register 1 have changed
0 No change in SECAM lock status SCM_LOCK_CHNG_Q
SECAM Lock
1 SECAM lock status has changed
x No change in PAL swinging
burst lock status
PAL_SW_LK_CHNG_Q
PAL swinging burst lock status
has changed
Reserved x Not used
0x4A Interrupt
Status 3
Read Only
Register
Register
Access
Page 2
Reserved x Not used
These bits
can be
cleared and
masked by
Register
0x4B and
Register
0x4C,
respectively.