Datasheet

ADV7189B
Rev. B | Page 69 of 104
Bit
Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes
0 Masks SD_LOCK_Q bit SD_LOCK_MSKB
1 Unmasks SD_LOCK_Q bit
0 Masks SD_UNLOCK_Q bit SD_UNLOCK_MSKB
1 Unmasks SD_UNLOCK_Q bit
Reserved 0 Not used
Reserved 0 Not used
Reserved 0 Not used
0 Masks SD_FR_CHNG_Q bit SD_FR_CHNG_MSKB
1 Unmasks SD_FR_CHNG_Q bit
0 Masks MV_PS_CS_Q bit MV_PS_CS_MSKB
1 Unmasks MV_PS_CS_Q bit
0x44 Interrupt
Mask 1
Read/Write
Register
Register
Access
Page 2
Reserved
x Not used
0x45 Reserved x x x x x x x x
0 Closed captioning not detected
in the input video signal
CCAPD_Q
1 Closed captioning data
detected in the video input
signal
0 Gemstar data not detected in
the input video signal
GEMD_Q
1 Gemstar data detected in the
input video signal
0 No change detected in CGMS
data in the input video signal
CGMS_CHNGD_Q
1 A change is detected in the
CGMS data in the input video
signal
0 No change detected in WSS
data in the input video signal
WSS_CHNGD_Q
1 A change is detected in the WSS
data in the input video signal
Reserved x Not used
Reserved x Not used
Reserved x Not used
0 Manual interrupt not set
0x46 Interrupt
Status 2
Read-Only
Register
Register
Access
Page 2
MPU_STIM_INTRQ_Q
1 Manual interrupt set
These bits
can be
cleared or
masked by
Register
0x47 and
Register
0x48,
respectively.
0 Do not clear CCAPD_CLR
1 Clears CCAPD_Q bit
0 Do not clear GEMD_CLR
1 Clears GEMD_Q bit
0 Do not clear CGMS_CHNGD_CLR
1 Clears CGMS_CHNGD_Q bit
0 Do not clear WSS_CHNGD_CLR
1 Clears WSS_CHNGD_Q bit
Reserved x Not used
Reserved x Not used
Reserved x Not used
0 Do not clear
0x47 Interrupt
Clear 2
Write-Only
Register
Access
Page 2
MPU_STIM_INTRQ_CLR
1 Clears MPU_STIM_INTRQ_Q bit