Datasheet

ADV7189B
Rev. B | Page 67 of 104
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SD Offset Cb SD_OFF_CB.7 SD_OFF_CB.6 SD_OFF_CB.5 SD_OFF_CB.4 SD_OFF_CB.3 SD_OFF_CB.2 SD_OFF_CB.1 SD_OFF_CB.0
SD Offset Cr SD_OFF_CR.7 SD_OFF_CR.6 SD_OFF_CR.5 SD_OFF_CR.4 SD_OFF_CR.3 SD_OFF_CR.2 SD_OFF_CR .1 SD_OFF_CR.0
SD Saturation
Cb
SD_SAT_CB.7 SD_SAT_CB.6 SD_SAT_CB.5 SD_SAT_CB.4 SD_SAT_CB.3 SD_SAT_CB.2 SD_SAT_CB.1 SD_SAT_CB.0
SD Saturation
Cr
SD_SAT_CR.7 SD_SAT_CR.6 SD_SAT_CR.5 SD_SAT_CR.4 SD_SAT_CR.3 SD_SAT_CR.2 SD_SAT_CR.1 SD_SAT_CR.0
NTSC V Bit
Begin
NVBEGDEL O NVBEGDEL E NVBEGSIGN NVBEG.4 NVBEG.3 NVBEG.2 NVBEG.1 NVBEG.0
NTSC V Bit End NVENDDEL O NVENDDEL E NVENDSIGN NVEND.4 NVEND.3 NVEND.2 NVEND.1 NVEND.0
NTSC F Bit
Toggle
NFTOGDEL O NFTOGDEL E NFTOGSIGN NFTOG.4 NFTOG.3 NFTOG.2 NFTOG.1 NFTOG.0
PAL V Bit Begin PVBEGDEL O PVBEGDEL E PVBEGSIGN PVBEG.4 PVBEG.3 PVBEG.2 PVBEG.1 PVBEG.0
PAL V Bit End PVENDDEL O PVENDDEL E PVENDSIGN PVEND.4 PVEND.3 PVEND.2 PVEND.1 PVEND.0
PAL F Bit Toggle PFTOGDEL O PFTOGDEL E PFTOGSIGN PFTOG.4 PFTOG.3 PFTOG.2 PFTOG.1 PFTOG.0
Reserved
Drive Strength DR_STR.1 DR_STR.0 DR_STR_C.1 DR_STR_C.0 DR_STR_S.1 DR_STR_S.0
Reserved
IF Comp Control IFFILTSEL.2 IFFILTSEL.1 IFFILTSEL.0
VS Mode
Control
VS_COAST_
MODE.1
VS_COAST_
MODE.0
EXTEND_VS_
MIN_FREQ
EXTEND_VS_
MAX_FREQ
IP
2
P
C REGISTER MAP DETAILS
The following registers are located in the Common 259HI2C Register Maps and Register Access sections, Page 2.
Table 84. Interrupt (Page 2) Register Map Details8F
1
Subaddress
Register Name
Reset
Value rw
Dec Hex
7 6 5 4 3 2 1 0
Interrupt Config 0 0001
x000
rw 64 0x40 INTRQ_DU
R_SEL.1
INTRQ_
DUR_SEL.0
MV_INTRQ
_SEL.1
MV_INTRQ
_SEL.0
MPU_STIM
_INTRQ
INTRQ_OP
_SEL.1
INTRQ_OP
_SEL.0
Reserved 65 0x41
Interrupt Status 1 r 66 0x42 MV_PS_
CS_Q
SD_FR_
CHNG_Q
SD_
UNLOCK_Q
SD_LOCK_
Q
Interrupt Clear 1 x000
0000
w 67 0x43 MV_PS_
CS_CLR
SD_FR_CH
NG_CLR
SD_UNLOCK
_CLR
SD_LOCK_
CLR
Interrupt Mask b1 x000
0000
rw 68 0x44 MV_PS_
CS_MSKB
SD_FR_CH
NG_MSKB
SD_UNLOCK
_MSKB
SD_LOCK_
MSKB
Reserved 69 0x45
Interrupt Status 2 r 70 0x46 MPU_STIM
_INTRQ_Q
WSS_CHN
GD_Q
CGMS_
CHNGD_Q
GEMD_Q CCAPD_Q
Interrupt Clear 2 0xxx
0000
w 71 0x47 MPU_STIM
_INTRQ_
CLR
WSS_
CHNGD_
CLR
CGMS_
CHNGD_
CLR
GEMD_CLR CCAPD_
CLR
Interrupt Mask b2 0xxx
0000
rw 72 0x48 MPU_
STIM_INTR
Q_MSKB
WSS_
CHNGD_
MSKB
CGMS_
CHNGD_
MSKB
GEMD_
MSKB
CCAPD_
MSKB
Raw Status 3 r 73 0x49 SCM_LOCK
SD_H_LOCK
SD_V_LOCK SD_OP_
50HZ
Interrupt Status 3 r 74 0x4A
PAL_SW_LK
_CHNG_Q
SCM_LOCK
_CHNG_Q
SD_AD_
CHNG_Q
SD_H_LOCK
_CHNG_Q
SD_V_LOCK
_CHNG_Q
SD_OP_
CHNG_Q
Interrupt Clear 3 xx00
0000
w 75 0x4B PAL_SW_L
K_CHNG_
CLR
SCM_LOCK
_CHNG_
CLR
SD_AD_CH
NG_CLR
SD_H_
LOCK_
CHNG_CLR
SD_V_LOCK
_CHNG_
CLR
SD_OP_
CHNG_CLR
Interrupt Mask b3 xx00
0000
rw 76 0x4C PAL_SW_
LK_CHNG_
MSKB
SCM_LOCK
_CHNG_
MSKB
SD_AD_
CHNG_
MSKB
SD_H_
LOCK_
CHNG_MSKB
SD_V_
LOCK_
CHNG_MSKB
SD_OP_
CHNG_MSKB
1
To access the interrupt register map, the register access page[1:0] bits in register address 0x0E must be programmed to 01b.