Datasheet

ADV7189B
Rev. B | Page 49 of 104
CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2[2]
For certain video sources, the CRC data bits can have an invalid
format. In such circumstances, the CRC checksum validation
procedure can be disabled. The CGMSD bit goes high if the
rising edge of the start bit is detected within a time window.
When CRC_ENABLE is 0, no CRC check is performed.
The CGMSD bit goes high if the rising edge of the start bit
is detected within a time window.
When CRC_ENABLE is 1 (default), CRC checksum is used to
validate the CGMS sequence. The CGMSD bit goes high for a
valid checksum. ADI recommended setting.
Wide Screen Signaling Data
WSS1[7:0], Address 0x91[7:0], WSS2[7:0], Address
0x92[7:0]
217HFigure 31 shows the bit correspondence between the analog
video waveform and the WSS1/WSS2 registers. WSS2[7:6]
are undetermined and should be masked out by software.
EDTV Data Registers
EDTV1[7:0], Address 0x93[7:0],
EDTV2[7:0], Address 0x94[7:0],
EDTV3[7:0], Address 0x95[7:0]
218HFigure 32 shows the bit correspondence between the analog
video waveform and the EDTV1/EDTV2/EDTV3 registers.
EDTV3[7:6] are undetermined and should be masked out by
software. EDTV3[5] is reserved for future use and, for now,
contains a 0. The three LSBs of the EDTV waveform are
currently not supported.
04983-0-031
ACTIVE
VIDEO
WSS2[5:0]WSS1[7:0]
RUN-IN
SEQUENCE
START
CODE
0 1 2 3 4 5 6 7 0 1 2 3 4 5
11.0μs
38.4μs
42.5μs
Figure 31. WSS Data Extraction
Table 58. WSS Access Information
Signal Name Register Location Address Register Default Value
WSS1[7:0] WSS 1[7:0] 145d 0x91 Readback Only
WSS2[5:0] WSS 2[5:0] 146d 0x92 Readback Only
EDTV1[7:0] EDTV2[7:0] EDTV3[5:0]
NOT SUPPORTED
01
3456701234567012345
2
04983-0-032
Figure 32. EDTV Data Extraction
Table 59. EDTV Access Information
Signal Name Register Location Address Register Default Value
EDTV1[7:0] EDTV 1[7:0] 147d 0x93 Readback Only
EDTV2[7:0] EDTV 2[7:0] 148d 0x94 Readback Only
EDTV3[7:0] EDTV 3[7:0] 149d 0x95 Readback Only