Datasheet

ADV7189B
Rev. B | Page 46 of 104
04983-0-027
FIELD 1
622 623 624
625
123 45 678 91011 2324
310 311 312
313
314 315 316 317 318 319 320 321 322 323 336 337
PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4
PFTOG[4:0] = 0x6
FIELD 2
OUTPUT
VIDEO
FIELD
OUTPUT
HS
OUTPUT
VS
OUTPUT
OUTPUT
VIDEO
FIELD
OUTPUT
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4
PFTOG[4:0] = 0x6
Figure 27. PAL Typical Vsync/Field Positions Using Register Writes in
216HTable 57
04983-0-028
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
VSYNC BEGIN
PVBEGSIGN
ODD FIELD?
01
NOYES
PVBEGDELO
VSBHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1 0
1 0
PVBEGDELE
VSBHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
10
10
NOT VALID FOR USER
PROGRAMMING
Figure 28. PAL Vsync Begin
PVBEGDELO PAL Vsync Begin Delay on Odd Field,
Address 0xE8[7]
When PVBEGDELO is 0 (default), there is no delay.
Setting PVBEGDELO to 1 delays Vsync going high on an odd
field by a line relative to PVBEG.
PVBEGDELE PAL Vsync Begin Delay on Even Field,
Address 0xE8[6]
When PVBEGDELE is 0, there is no delay.
Setting PVBEGDELE to 1 (default) delays Vsync going high on
an even field by a line relative to PVBEG.
PVBEGSIGN PAL Vsync Begin Sign, Address 0xE8[5]
Setting PVBEGSIGN to 0 delays the beginning of Vsync. Set for
user manual programming.
Setting PVBEGSIGN to 1 (default) advances the beginning of
Vsync. Not recommended for user programming.
PVBEG[4:0] PAL Vsync Begin, Address 0xE8[4:0]
The default value of PVBEG is 00101, indicating the PAL Vsync
begin position.
For all NTSC/PAL Vsync timing controls, both the V bit in the
AV code and the Vsync on the VS pin are modified.