Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- REVISION HISTORY
- INTRODUCTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- ANALOG FRONT END
- ANALOG INPUT MUXING
- MANUAL INPUT MUXING
- XTAL CLOCK INPUT PIN FUNCTIONALITY
- 28.63636 MHz CRYSTAL OPERATION
- ANTIALIASING FILTERS
- SCART AND FAST BLANKING
- FAST BLANK CONTROL
- FB_MODE [1:0], Address 0xED [1:0]
- Static Mux Selection Control
- Alpha Blend Coefficient
- Fast Blank Edge Shaping
- Contrast Reduction
- Contrast Reduction Enable
- Contrast Mode
- Fast Blank and Contrast Reduction Programmable Thresholds
- FB_INV, Address 0xED [3], Write Only
- Readback of FB Pin Status
- FB Timing
- Alignment of FB Signal
- Color Space Converter Manual Adjust
- GLOBAL CONTROL REGISTERS
- STANDARD DEFINITION PROCESSOR (SDP)
- SD LUMA PATH
- SD CHROMA PATH
- SYNC PROCESSING
- VBI DATA RECOVERY
- GENERAL SETUP
- Video Standard Selection
- Autodetection of SD Modes
- VID_SEL [3:0], Address 0x00 [7:4]
- AD_SEC525_EN, SECAM 525 Autodetect Enable, Address 0x07 [7]
- AD_SECAM_EN, SECAM Autodetect Enable, Address 0x07 [6]
- AD_N443_EN, NTSC 443 Autodetect Enable, Address 0x07 [5]
- AD_P60_EN, PAL 60 Autodetect Enable, Address 0x07 [4]
- AD_PALN_EN, PAL N Autodetect Enable, Address 0x07 [3]
- AD_PALM_EN, PAL M Autodetect Enable, Address 0x07 [2]
- AD_NTSC_EN, NTSC Autodetect Enable, Address 0x07 [1]
- AD_PAL_EN, PAL (B/G/I/H) Autodetect Enable, Address 0x07 [0]
- Subcarrier Frequency Lock Inversion
- Lock-Related Controls
- VS_COAST_MODE [1:0], Address 0xF9 [3:2]
- ST_NOISE_VLD, Sync Tip Noise Measurement Valid, Address 0xDE [3], Read Only
- ST_NOISE [10:0], Sync Tip Noise Measurement, Addresses 0xDE [2:0], 0xDF [7:0]
- COLOR CONTROLS
- CON [7:0], Contrast Adjust, Address 0x08 [7:0]
- SD_SAT_CB [7:0], SD Saturation Cb Channel, Address 0xE3 [7:0]
- SD_SAT_CR [7:0], SD Saturation Cr Channel, Address 0xE4 [7:0]
- SD_OFF_CB [7:0], SD Offset Cb Channel, Address 0xE1 [7:0]
- SD_OFF_CR [7:0], SD Offset Cr Channel, Address 0xE2 [7:0]
- BRI [7:0], Brightness Adjust, Address 0x0A [7:0]
- HUE [7:0], Hue Adjust, Address 0x0B [7:0]
- DEF_Y [5:0], Default Value Y, Address 0x0C [7:2]
- DEF_C [7:0], Default Value C, Address 0x0D [7:0]
- DEF_VAL_EN, Default Value Enable, Address 0x0C [0]
- DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1]
- CLAMP OPERATION
- LUMA FILTER
- CHROMA FILTER
- GAIN OPERATION
- Luma Gain
- Chroma Gain
- CAGC [1:0], Chroma Automatic Gain Control, Address 0x2C [1:0]
- CAGT [1:0], Chroma Automatic Gain Timing, Address 0x2D [7:6]
- CMG [11:0]/CG [11:0], Chroma Manual Gain/Chroma Gain, Address 0x2D [3:0], Address 0x2E [7:0]
- CKE, Color-Kill Enable, Address 0x2B [6]
- CKILLTHR [2:0], Color-Kill Threshold, Address 0x3D [6:4]
- CHROMA TRANSIENT IMPROVEMENT (CTI)
- DIGITAL NOISE REDUCTION (DNR) AND LUMA PEAKING FILTER
- COMB FILTERS
- NTSC Comb Filter Settings
- PAL Comb Filter Settings
- Vertical Blank Control
- NVBIOLCM [1:0], NTSC VBI Odd Field Luma Comb Mode, Address 0xEB [7:6]
- NVBIELCM [1:0], NTSC VBI Even Field Luma Comb Mode, Address 0xEB [5:4]
- PVBIOLCM [1:0], PAL VBI Odd Field Luma Comb Mode, Address 0xEB [3:2]
- PVBIELCM [1:0], PAL VBI Even Field Luma Comb Mode, Address 0xEB [1:0]
- NVBIOCCM [1:0], NTSC VBI Odd Field Chroma Comb Mode, Address 0xEC [7:6]
- NVBIECCM [1:0], NTSC VBI Even Field Chroma Comb Mode, Address 0xEC [5:4]
- PVBIOCCM [1:0], PAL VBI Odd Field Chroma Comb Mode, Address 0xEC [3:2]
- PVBIECCM [1:0], PAL VBI Even Field Chroma Comb Mode, Address 0xEC [1:0]
- AV CODE INSERTION AND CONTROLS
- BT656-4, ITU-R BT.656-4 Enable, Address 0x04 [7]
- SD_DUP_AV, Duplicate AV Codes, Address 0x03 [0]
- VBI_EN, Vertical Blanking Interval Data Enable, Address 0x03 [7]
- BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2]
- RANGE, Range Selection, Address 0x04 [0]
- AUTO_PDC_EN, Automatic Programmed Delay Control, Address 0x27 [6]
- LTA [1:0], Luma Timing Adjust, Address 0x27 [1:0]
- CTA [2:0], Chroma Timing Adjust, Address 0x27 [5:3]
- SYNCHRONIZATION OUTPUT SIGNALS
- HS Configuration
- VS and FIELD Configuration
- NEWAVMODE, New AV Mode, Address 0x31 [4]
- HVSTIM, Horizontal VS Timing, Address 0x31 [3]
- VSBHO, VS Begin Horizontal Position Odd, Address 0x32 [7]
- VSBHE, VS Begin Horizontal Position Even, Address 0x32 [6]
- VSEHO VS, End Horizontal Position Odd, Address 0x33 [7]
- VSEHE, VS End Horizontal Position Even, Address 0x33 [6]
- PVS, Polarity VS, Address 0x37 [5]
- PF, Polarity FIELD, Address 0x37 [3]
- NVBEGDELO, NTSC Vsync Begin Delay on Odd Field, Address 0xE5 [7]
- NVBEGDELE, NTSC Vsync Begin Delay on Even Field, Address 0xE5 [6]
- NVBEGSIGN, NTSC Vsync Begin Sign, Address 0xE5 [5]
- NVBEG [4:0], NTSC Vsync Begin, Address 0xE5 [4:0]
- NVENDDELO, NTSC Vsync End Delay on Odd Field, Address 0xE6 [7]
- NVENDDELE, NTSC Vsync End Delay on Even Field, Address 0xE6 [6]
- NVENDSIGN, NTSC Vsync End Sign, Address 0xE6 [5]
- NVEND [4:0], NTSC Vsync End, Address 0xE6 [4:0]
- NFTOGDELO, NTSC Field Toggle Delay on Odd Field, Address 0xE7 [7]
- NFTOGDELE, NTSC Field Toggle Delay on Even Field, Address 0xE7 [6]
- NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]
- NFTOG [4:0], NTSC Field Toggle, Address 0xE7 [4:0]
- PVBEGDELO, PAL Vsync Begin Delay on Odd Field, Address 0xE8 [7]
- PVBEGDELE, PAL Vsync Begin Delay on Even Field, Address 0xE8 [6]
- PVBEGSIGN, PAL Vsync Begin Sign, Address 0xE8 [5]
- PVBEG [4:0], PAL Vsync Begin, Address 0xE8 [4:0]
- PVENDDELO, PAL Vsync End Delay on Odd Field, Address 0xE9 [7]
- PVENDDELE, PAL Vsync End Delay on Even Field, Address 0xE9 [6]
- PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]
- PVEND [4:0], PAL Vsync End, Address 0xE9 [4:0]
- PFTOGDELO, PAL Field Toggle Delay on Odd Field, Address 0xEA [7]
- PFTOGDELE, PAL Field Toggle Delay on Even Field, Address 0xEA [6]
- PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]
- PFTOG, PAL Field Toggle, Address 0xEA [4:0]
- SYNC PROCESSING
- VBI DATA DECODE
- VDP Default Configuration
- VDP Manual Configuration
- MAN_LINE_PGM, Enable Manual Line Programming of VBI Standards, Address 0x64 [7], User Sub Map
- VBI_DATA_Px_Ny [3:0], VBI Standard to be Decoded on Line x for PAL, Line y for NTSC, Addresses 0x64 to 0x77, User Sub Map
- VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual Selection of Teletext Type, Address 0x60 [2], User Sub Map
- VDP_TTXT_TYPE_MAN [1:0], Specify the Teletext Type, Address 0x60 [1:0], User Sub Map
- VDP Ancillary Data Output
- ADF_ENABLE, Enable Ancillary Data Output Through 656 Stream, Address 0x62 [7], User Sub Map
- ADF_DID [4:0], User-Specified Data ID Word in Ancillary Data, Address 0x62 [4:0], User Sub Map
- ADF_SDID [5:0], User-Specified Secondary Data ID Word in Ancillary Data, Address 0x63 [5:0], User Sub Map
- DUPLICATE_ADF, Enable Duplication/Spreading of Ancillary Data over Y and C Buses, Address 0x63 [7], User Sub Map
- ADF_MODE [1:0], Determine the Ancillary Data Output Mode, Address 0x62 [6:5], User Sub Map
- Structure of VBI Words in Ancillary Data Stream
- VDP Framing Code
- I2C INTERFACE
- STANDARD DETECTION AND IDENTIFICATION
- Notes
- STDI_DVALID, Standard Identification Data Valid Read Back, Address 0xB1 [7]
- STDI_LINE_COUNT_MODE, Address 0x86 [3]
- BL [13:0], Block Length Readback, Address 0xB1 [5:0], Address 0xB2 [7:0]
- LCVS [4:0], Line Count in Vsync Readback, Address 0xB3 [7:3]
- LCF [10:0], Line Count in Field Readback, Address 0xB3 [2:0], Address 0xB4 [7:0]
- FCL [12:0], 1/256th of Field Length in Number of Crystal Clocks Read back, Address 0xCA [4:0], Address 0xCB [7:0]
- STDI Readback Values for SD, PR, and HD
- I2C READBACK REGISTERS
- Teletext
- CGMS and WSS
- CC
- CC_CLEAR, Closed Captioning Clear, Address 0x78 [0], User Sub Map, Write Only, Self-Clearing
- CC_AVL, Closed Captioning Available, Address 0x78 [0], User Sub Map, Read Only
- CC_EVEN_FIELD, Address 0x78 [1], User Sub Map, Read Only
- VDP_CCAP_DATA_0, Address 0x79 [7:0], User Sub Map, Read Only
- VDP_CCAP_DATA_1, Address 0x7A [7:0], User Sub Map, Read Only
- VITC
- VPS/PDC/UTC/Gemstar
- I2C_GS_VPS_PDC_UTC (VDP) [1:0], Address 0x9C [6:5], User Sub Map
- GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear, Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
- GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available, Address 0x78 [4], User Sub Map, Read Only
- VDP_GS_VPS_PDC_UTC Readback Registers, Addresses 0x84 to 0x90, User Sub Map
- VPS
- Gemstar
- AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map
- GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only
- PDC/UTC
- VBI System 2
- Gemstar Data Recovery
- GDE_SEL_OLD_ADF, Address 0x4C [3], User Map
- Gemstar Bit Names
- Gemstar 2× Format, Half-Byte Output Mode
- Gemstar 1× Format, Half-Byte Output Mode
- NTSC CC Data
- PAL CC Data
- GDECEL [15:0], Gemstar Decoding Even Lines, Address 0x48 [7:0], Address 0x49 [7:0]
- GDECOL [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0]
- GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0]
- Letterbox Detection
- Detection at the Start of a Field
- Detection at the End of a Field
- Detection at the Midrange
- LB_LCT [7:0], Letterbox Line Count Top, Address 0x9B [7:0]; LB_LCM [7:0], Letterbox Line Count Mid, Address 0x9C [7:0]; LB_LCB [7:0], Letterbox Line Count Bottom, Address 0x9D [7:0]
- LB_TH [4:0], Letterbox Threshold Control, Address 0xDC [4:0]
- LB_SL [3:0], Letterbox Start Line, Address 0xDD [7:4]
- LB_EL [3:0], Letterbox End Line, Address 0xDD [3:0]
- IF Compensation Filter
- I2C Interrupt System
- Interrupt Request Output Operation
- INTRQ_DUR_SEL [1:0], Interrupt Duration Select, Address 0x40 [7:6], User Sub Map
- Interrupt Drive Level
- INTRQ_OP_SEL [1:0], Interrupt Duration Select, Address 0x40 [1:0], User Sub Map
- Multiple Interrupt Events
- Macrovision Interrupt Selection Bits
- MV_INTRQ_SEL [1:0], Macrovision Interrupt Selection Bits, Address 0x40 [5:4], User Sub Map
- PIXEL PORT CONFIGURATION
- MPU PORT DESCRIPTION
- I2C REGISTER MAPS
- PCB LAYOUT RECOMMENDATIONS
- TYPICAL CIRCUIT CONNECTION
- OUTLINE DIMENSIONS
ADV7188
Rev. A | Page 99 of 112
USER SUB MAP
The collective name for the subaddress registers in Table 106 is user sub map. To access the user sub map, SUB_USR_EN in Register
Address 0x0E (user map) must be programmed to 1.
Table 106. User Sub Map Register Details
Address
Dec Hex Register Name RW 7 6 5 4 3 2 1 0
Reset
Value
(Hex)
64 40 Interrupt
Configuration 0
RW INTRQ_DUR_
SEL.1
INTRQ_DUR_
SEL.0
MV_INTRQ_
SEL.1
MV_INTRQ_
SEL.0
MPU_STIM_I
NTRQ
INTRQ_OP_SEL.1 INTRQ_OP_SEL.0 0001x000 10
66 42 Interrupt Status 1 R MV_PS_CS_Q SD_FR_
HNG_Q
SD_UNLOCK_Q SD_LOCK_Q – –
67 43 Interrupt Clear 1 W MV_PS_CS_CLR SD_FR_
CHNG_CLR
SD_UNLOCK_CLR SD_LOCK_CLR x0000000 00
68 44 Interrupt Mask 1 RW MV_PS_CS_MSKB SD_FR_CHNG_
MSKB
SD_UNLOCK_
MSKB
SD_LOCK_MSKB x0000000 00
69 45 Raw Status 2 R MPU_STIM_INTRQ EVEN_FIELD CCAPD – –
70 46 Interrupt Status 2 R MPU_STIM_INTRQ_Q SD_FIELD_
CHNGD_Q
GEMD_Q CCAPD_Q – –
71 47 Interrupt Clear 2 W MPU_STIM_
INTRQ_CLR
SD_FIELD_
CHNGD_CLR
GEMD_CLR CCAPD_CLR 0xx00000 00
72 48 Interrupt Mask 2 RW MPU_STIM_
INTRQ_MSKB
SD_FIELD_
CHNGD_MSKB
GEMD_MSKB CCAPD_MSKB 0xx00000 00
73 49 Raw Status 3 R SCM_LOCK SD_H_LOCK SD_V_LOCK SD_OP_50Hz – –
74 4A Interrupt Status 3 R PAL_SW_LK_
CHNG_Q
SCM_LOCK_
CHNG_Q
SD_AD_CHNG_Q SD_H_LOCK_
CHNG_Q
SD_V_LOCK_
CHNG_Q
SD_OP_CHNG_Q – –
75 4B Interrupt Clear 3 W PAL_SW_LK_
CHNG_CLR
SCM_LOCK_
CHNG_CLR
SD_AD_CHNG_
CLR
SD_H_LOCK_
CHNG_CLR
SD_V_LOCK_
CHNG_CLR
SD_OP_
CHNG_CLR
xx000000 00
76 4C Interrupt Mask 3 RW PAL_SW_LK_
CHNG_MSKB
SCM_LOCK_
CHNG_MSKB
SD_AD_CHNG_
MSKB
SD_H_LOCK_
CHNG_MSKB
SD_V_LOCK_
CHNG_MSKB
SD_OP_
CHNG_MSKB
xx000000 00
78 4E Interrupt Status 4 R VDP_VITC_Q VDP_GS_VPS_
PDC_UTC_
CHNG_Q
VDP_
CGMS_WSS_
CHNGD_Q
VDP_CCAPD_Q – –
79 4F Interrupt Clear 4 W VDP_VITC_CLR VDP_GS_VPS_
PDC_UTC_
CHNG_CLR
VDP_CGMS_WSS_
CHNGD_CLR
VDP_CCAPD_CLR 00x0x0x0 00
80 50 Interrupt Mask 4 RW VDP_VITC_MSKB VDP_GS_VPS_
PDC_UTC_
CHNG_MSKB
VDP_CGMS_WSS_
CHNGD_MSKB
VDP_CCAPD_
MSKB
00x0x0x0 00
96 60 VDP_Config_1 RW WST_PKT_
DECOD_
DISABLE
VDP_TTXT_TYPE_
MAN_ENABLE
VDP_TTXT_TYPE_
MAN.1
VDP_TTXT_
TYPE_MAN.0
10001000 88
97 61 VDP_Config_2 RW AUTO_DETECT_
GS_TYPE
0001xx00 10
98 62 VDP_ADF_
Config_1
RW ADF_ENABLE ADF_MODE.1 ADF_MODE.0 ADF_DID.4 ADF_DID.3 ADF_DID.2 ADF_DID.1 ADF_DID.0 00010101 15
99 63 VDP_ADF_
Config_2
RW DUPLICATE ADF ADF_SDID.5 ADF_SDID.4 ADF_SDID.3 ADF_SDID.2 ADF_SDID.1 ADF_SDID.0 0x101010 2A
100 64 VDP_LINE_00E RW MAN_LINE_PGM VBI_DATA_
P318.3
VBI_DATA_
P318.2
VBI_DATA_
P318.1
VBI_DATA_
P318.0
0xxx0000 00
101 65 VDP_LINE_00F RW VBI_DATA_
P6_N23.3
VBI_DATA_P6_
N23.2
VBI_DATA_P6_
N23.1
VBI_DATA_P6_
N23.0
VBI_DATA_P319_
N286.3
VBI_DATA_P319_
N286.2
VBI_DATA_P319_
N286.1
VBI_DATA_P319_
N286.0
00000000 00
102 66 VDP_LINE_010 RW VBI_DATA_
P7_N24.3
VBI_DATA_P7_
N24.2
VBI_DATA_P7_
N24.1
VBI_DATA_P7_
N24.0
VBI_DATA_P320_
N287.3
VBI_DATA_P320_
N287.2
VBI_DATA_P320_
N287.1
VBI_DATA_P320_
N287.0
00000000 00
103 67 VDP_LINE_011 RW VBI_DATA_
P8_N25.3
VBI_DATA_P8_
N25.2
VBI_DATA_P8_
N25.1
VBI_DATA_P8_
N25.0
VBI_DATA_P321_
N288.3
VBI_DATA_P321_
N288.2
VBI_DATA_P321_
N288.1
VBI_DATA_P321_
N288.0
00000000 00
104 68 VDP_LINE_012 RW VBI_DATA_
P9.3
VBI_DATA_P9.2 VBI_DATA_P9.1 VBI_DATA_P9.0 VBI_DATA_
P322.3
VBI_DATA_P322.2 VBI_DATA_
P322.1
VBI_DATA_P322.0 00000000 00
105 69 VDP_LINE_013 RW VBI_DATA_
P10.3
VBI_DATA_P10.2 VBI_DATA_P10.1 VBI_DATA_P10.0 VBI_DATA_P323.3 VBI_DATA_P323.2 VBI_DATA_
P323.1
VBI_DATA_P323.0 00000000 00
106 6A VDP_LINE_014 RW VBI_DATA_
P11.3
VBI_DATA_P11.2 VBI_DATA_P11.1 VBI_DATA_P11.0 VBI_DATA_P324_
N272.3
VBI_DATA_P324_
N272.2
VBI_DATA_P324_
N272.1
VBI_DATA_P324_
N272.0
00000000 00
107 6B VDP_LINE_015 RW VBI_DATA_
P12_N10.3
VBI_DATA_P12_
N10.2
VBI_DATA_P12_
N10.1
VBI_DATA_P12_
N10.0
VBI_DATA_P325_
N273.3
VBI_DATA_P325_
N273.2
VBI_DATA_P325_
N273.1
VBI_DATA_P325_
N273.0
00000000 00
108 6C VDP_LINE_016 RW VBI_DATA_
P13_N11.3
VBI_DATA_P13_
N11.2
VBI_DATA_P13_
N11.1
VBI_DATA_P13_
N11.0
VBI_DATA_P326_
N274.3
VBI_DATA_P326_
N274.2
VBI_DATA_P326_
N274.1
VBI_DATA_P326_
N274.0
00000000 00
109 6D VDP_LINE_017 RW VBI_DATA_
P14_N12.3
VBI_DATA_P14_
N12.2
VBI_DATA_P14_
N12.1
VBI_DATA_P14_
N12.0
VBI_DATA_P327_
N275.3
VBI_DATA_P327_
N275.2
VBI_DATA_P327_
N275.1
VBI_DATA_P327_
N275.0
00000000 00
110 6E VDP_LINE_018 RW VBI_DATA_
P15_N13.3
VBI_DATA_P15_
N13.2
VBI_DATA_P15_
N13.1
VBI_DATA_P15_
N13.0
VBI_DATA_P328_
N276.3
VBI_DATA_P328_
N276.2
VBI_DATA_P328_
N276.1
VBI_DATA_P328_
N276.0
00000000 00
111 6F VDP_LINE_019 RW VBI_DATA_
P16_N14.3
VBI_DATA_P16_
N14.2
VBI_DATA_P16_
N14.1
VBI_DATA_P16_
N14.0
VBI_DATA_P329_
N277.3
VBI_DATA_P329_
N277.2
VBI_DATA_P329_
N277.1
VBI_DATA_P329_
N277.0
00000000 00
112 70 VDP_LINE_01A RW VBI_DATA_
P17_N15.3
VBI_DATA_P17_
N15.2
VBI_DATA_P17_
N15.1
VBI_DATA_P17_
N15.0
VBI_DATA_P330_
N278.3
VBI_DATA_P330_
N278.2
VBI_DATA_P330_
N278.1
VBI_DATA_P330_
N278.0
00000000 00
113 71 VDP_LINE_01B RW VBI_DATA_
P18_N16.3
VBI_DATA_P18_
N16.2
VBI_DATA_P18_
N16.1
VBI_DATA_P18_
N16.0
VBI_DATA_P331_
N279.3
VBI_DATA_P331_
N279.2
VBI_DATA_P331_
N279.1
VBI_DATA_P331_
N279.0
00000000 00
114 72 VDP_LINE_01C RW VBI_DATA_
P19_N17.3
VBI_DATA_P19_
N17.2
VBI_DATA_P19_
N17.1
VBI_DATA_P19_
N17.0
VBI_DATA_P332_
N280.3
VBI_DATA_P332_
N280.2
VBI_DATA_P332_
N280.1
VBI_DATA_
P332_N280.0
00000000 00
115 73 VDP_LINE_01D RW VBI_DATA_
P20_N18.3
VBI_DATA_P20_
N18.2
VBI_DATA_P20_
N18.1
VBI_DATA_P20_
N18.0
VBI_DATA_P333_
N281.3
VBI_DATA_P333_
N281.2
VBI_DATA_P333_
N281.1
VBI_DATA_
P333_N281.0
00000000 00