Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- REVISION HISTORY
- INTRODUCTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- ANALOG FRONT END
- ANALOG INPUT MUXING
- MANUAL INPUT MUXING
- XTAL CLOCK INPUT PIN FUNCTIONALITY
- 28.63636 MHz CRYSTAL OPERATION
- ANTIALIASING FILTERS
- SCART AND FAST BLANKING
- FAST BLANK CONTROL
- FB_MODE [1:0], Address 0xED [1:0]
- Static Mux Selection Control
- Alpha Blend Coefficient
- Fast Blank Edge Shaping
- Contrast Reduction
- Contrast Reduction Enable
- Contrast Mode
- Fast Blank and Contrast Reduction Programmable Thresholds
- FB_INV, Address 0xED [3], Write Only
- Readback of FB Pin Status
- FB Timing
- Alignment of FB Signal
- Color Space Converter Manual Adjust
- GLOBAL CONTROL REGISTERS
- STANDARD DEFINITION PROCESSOR (SDP)
- SD LUMA PATH
- SD CHROMA PATH
- SYNC PROCESSING
- VBI DATA RECOVERY
- GENERAL SETUP
- Video Standard Selection
- Autodetection of SD Modes
- VID_SEL [3:0], Address 0x00 [7:4]
- AD_SEC525_EN, SECAM 525 Autodetect Enable, Address 0x07 [7]
- AD_SECAM_EN, SECAM Autodetect Enable, Address 0x07 [6]
- AD_N443_EN, NTSC 443 Autodetect Enable, Address 0x07 [5]
- AD_P60_EN, PAL 60 Autodetect Enable, Address 0x07 [4]
- AD_PALN_EN, PAL N Autodetect Enable, Address 0x07 [3]
- AD_PALM_EN, PAL M Autodetect Enable, Address 0x07 [2]
- AD_NTSC_EN, NTSC Autodetect Enable, Address 0x07 [1]
- AD_PAL_EN, PAL (B/G/I/H) Autodetect Enable, Address 0x07 [0]
- Subcarrier Frequency Lock Inversion
- Lock-Related Controls
- VS_COAST_MODE [1:0], Address 0xF9 [3:2]
- ST_NOISE_VLD, Sync Tip Noise Measurement Valid, Address 0xDE [3], Read Only
- ST_NOISE [10:0], Sync Tip Noise Measurement, Addresses 0xDE [2:0], 0xDF [7:0]
- COLOR CONTROLS
- CON [7:0], Contrast Adjust, Address 0x08 [7:0]
- SD_SAT_CB [7:0], SD Saturation Cb Channel, Address 0xE3 [7:0]
- SD_SAT_CR [7:0], SD Saturation Cr Channel, Address 0xE4 [7:0]
- SD_OFF_CB [7:0], SD Offset Cb Channel, Address 0xE1 [7:0]
- SD_OFF_CR [7:0], SD Offset Cr Channel, Address 0xE2 [7:0]
- BRI [7:0], Brightness Adjust, Address 0x0A [7:0]
- HUE [7:0], Hue Adjust, Address 0x0B [7:0]
- DEF_Y [5:0], Default Value Y, Address 0x0C [7:2]
- DEF_C [7:0], Default Value C, Address 0x0D [7:0]
- DEF_VAL_EN, Default Value Enable, Address 0x0C [0]
- DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1]
- CLAMP OPERATION
- LUMA FILTER
- CHROMA FILTER
- GAIN OPERATION
- Luma Gain
- Chroma Gain
- CAGC [1:0], Chroma Automatic Gain Control, Address 0x2C [1:0]
- CAGT [1:0], Chroma Automatic Gain Timing, Address 0x2D [7:6]
- CMG [11:0]/CG [11:0], Chroma Manual Gain/Chroma Gain, Address 0x2D [3:0], Address 0x2E [7:0]
- CKE, Color-Kill Enable, Address 0x2B [6]
- CKILLTHR [2:0], Color-Kill Threshold, Address 0x3D [6:4]
- CHROMA TRANSIENT IMPROVEMENT (CTI)
- DIGITAL NOISE REDUCTION (DNR) AND LUMA PEAKING FILTER
- COMB FILTERS
- NTSC Comb Filter Settings
- PAL Comb Filter Settings
- Vertical Blank Control
- NVBIOLCM [1:0], NTSC VBI Odd Field Luma Comb Mode, Address 0xEB [7:6]
- NVBIELCM [1:0], NTSC VBI Even Field Luma Comb Mode, Address 0xEB [5:4]
- PVBIOLCM [1:0], PAL VBI Odd Field Luma Comb Mode, Address 0xEB [3:2]
- PVBIELCM [1:0], PAL VBI Even Field Luma Comb Mode, Address 0xEB [1:0]
- NVBIOCCM [1:0], NTSC VBI Odd Field Chroma Comb Mode, Address 0xEC [7:6]
- NVBIECCM [1:0], NTSC VBI Even Field Chroma Comb Mode, Address 0xEC [5:4]
- PVBIOCCM [1:0], PAL VBI Odd Field Chroma Comb Mode, Address 0xEC [3:2]
- PVBIECCM [1:0], PAL VBI Even Field Chroma Comb Mode, Address 0xEC [1:0]
- AV CODE INSERTION AND CONTROLS
- BT656-4, ITU-R BT.656-4 Enable, Address 0x04 [7]
- SD_DUP_AV, Duplicate AV Codes, Address 0x03 [0]
- VBI_EN, Vertical Blanking Interval Data Enable, Address 0x03 [7]
- BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2]
- RANGE, Range Selection, Address 0x04 [0]
- AUTO_PDC_EN, Automatic Programmed Delay Control, Address 0x27 [6]
- LTA [1:0], Luma Timing Adjust, Address 0x27 [1:0]
- CTA [2:0], Chroma Timing Adjust, Address 0x27 [5:3]
- SYNCHRONIZATION OUTPUT SIGNALS
- HS Configuration
- VS and FIELD Configuration
- NEWAVMODE, New AV Mode, Address 0x31 [4]
- HVSTIM, Horizontal VS Timing, Address 0x31 [3]
- VSBHO, VS Begin Horizontal Position Odd, Address 0x32 [7]
- VSBHE, VS Begin Horizontal Position Even, Address 0x32 [6]
- VSEHO VS, End Horizontal Position Odd, Address 0x33 [7]
- VSEHE, VS End Horizontal Position Even, Address 0x33 [6]
- PVS, Polarity VS, Address 0x37 [5]
- PF, Polarity FIELD, Address 0x37 [3]
- NVBEGDELO, NTSC Vsync Begin Delay on Odd Field, Address 0xE5 [7]
- NVBEGDELE, NTSC Vsync Begin Delay on Even Field, Address 0xE5 [6]
- NVBEGSIGN, NTSC Vsync Begin Sign, Address 0xE5 [5]
- NVBEG [4:0], NTSC Vsync Begin, Address 0xE5 [4:0]
- NVENDDELO, NTSC Vsync End Delay on Odd Field, Address 0xE6 [7]
- NVENDDELE, NTSC Vsync End Delay on Even Field, Address 0xE6 [6]
- NVENDSIGN, NTSC Vsync End Sign, Address 0xE6 [5]
- NVEND [4:0], NTSC Vsync End, Address 0xE6 [4:0]
- NFTOGDELO, NTSC Field Toggle Delay on Odd Field, Address 0xE7 [7]
- NFTOGDELE, NTSC Field Toggle Delay on Even Field, Address 0xE7 [6]
- NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]
- NFTOG [4:0], NTSC Field Toggle, Address 0xE7 [4:0]
- PVBEGDELO, PAL Vsync Begin Delay on Odd Field, Address 0xE8 [7]
- PVBEGDELE, PAL Vsync Begin Delay on Even Field, Address 0xE8 [6]
- PVBEGSIGN, PAL Vsync Begin Sign, Address 0xE8 [5]
- PVBEG [4:0], PAL Vsync Begin, Address 0xE8 [4:0]
- PVENDDELO, PAL Vsync End Delay on Odd Field, Address 0xE9 [7]
- PVENDDELE, PAL Vsync End Delay on Even Field, Address 0xE9 [6]
- PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]
- PVEND [4:0], PAL Vsync End, Address 0xE9 [4:0]
- PFTOGDELO, PAL Field Toggle Delay on Odd Field, Address 0xEA [7]
- PFTOGDELE, PAL Field Toggle Delay on Even Field, Address 0xEA [6]
- PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]
- PFTOG, PAL Field Toggle, Address 0xEA [4:0]
- SYNC PROCESSING
- VBI DATA DECODE
- VDP Default Configuration
- VDP Manual Configuration
- MAN_LINE_PGM, Enable Manual Line Programming of VBI Standards, Address 0x64 [7], User Sub Map
- VBI_DATA_Px_Ny [3:0], VBI Standard to be Decoded on Line x for PAL, Line y for NTSC, Addresses 0x64 to 0x77, User Sub Map
- VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual Selection of Teletext Type, Address 0x60 [2], User Sub Map
- VDP_TTXT_TYPE_MAN [1:0], Specify the Teletext Type, Address 0x60 [1:0], User Sub Map
- VDP Ancillary Data Output
- ADF_ENABLE, Enable Ancillary Data Output Through 656 Stream, Address 0x62 [7], User Sub Map
- ADF_DID [4:0], User-Specified Data ID Word in Ancillary Data, Address 0x62 [4:0], User Sub Map
- ADF_SDID [5:0], User-Specified Secondary Data ID Word in Ancillary Data, Address 0x63 [5:0], User Sub Map
- DUPLICATE_ADF, Enable Duplication/Spreading of Ancillary Data over Y and C Buses, Address 0x63 [7], User Sub Map
- ADF_MODE [1:0], Determine the Ancillary Data Output Mode, Address 0x62 [6:5], User Sub Map
- Structure of VBI Words in Ancillary Data Stream
- VDP Framing Code
- I2C INTERFACE
- STANDARD DETECTION AND IDENTIFICATION
- Notes
- STDI_DVALID, Standard Identification Data Valid Read Back, Address 0xB1 [7]
- STDI_LINE_COUNT_MODE, Address 0x86 [3]
- BL [13:0], Block Length Readback, Address 0xB1 [5:0], Address 0xB2 [7:0]
- LCVS [4:0], Line Count in Vsync Readback, Address 0xB3 [7:3]
- LCF [10:0], Line Count in Field Readback, Address 0xB3 [2:0], Address 0xB4 [7:0]
- FCL [12:0], 1/256th of Field Length in Number of Crystal Clocks Read back, Address 0xCA [4:0], Address 0xCB [7:0]
- STDI Readback Values for SD, PR, and HD
- I2C READBACK REGISTERS
- Teletext
- CGMS and WSS
- CC
- CC_CLEAR, Closed Captioning Clear, Address 0x78 [0], User Sub Map, Write Only, Self-Clearing
- CC_AVL, Closed Captioning Available, Address 0x78 [0], User Sub Map, Read Only
- CC_EVEN_FIELD, Address 0x78 [1], User Sub Map, Read Only
- VDP_CCAP_DATA_0, Address 0x79 [7:0], User Sub Map, Read Only
- VDP_CCAP_DATA_1, Address 0x7A [7:0], User Sub Map, Read Only
- VITC
- VPS/PDC/UTC/Gemstar
- I2C_GS_VPS_PDC_UTC (VDP) [1:0], Address 0x9C [6:5], User Sub Map
- GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear, Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
- GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available, Address 0x78 [4], User Sub Map, Read Only
- VDP_GS_VPS_PDC_UTC Readback Registers, Addresses 0x84 to 0x90, User Sub Map
- VPS
- Gemstar
- AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map
- GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only
- PDC/UTC
- VBI System 2
- Gemstar Data Recovery
- GDE_SEL_OLD_ADF, Address 0x4C [3], User Map
- Gemstar Bit Names
- Gemstar 2× Format, Half-Byte Output Mode
- Gemstar 1× Format, Half-Byte Output Mode
- NTSC CC Data
- PAL CC Data
- GDECEL [15:0], Gemstar Decoding Even Lines, Address 0x48 [7:0], Address 0x49 [7:0]
- GDECOL [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0]
- GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0]
- Letterbox Detection
- Detection at the Start of a Field
- Detection at the End of a Field
- Detection at the Midrange
- LB_LCT [7:0], Letterbox Line Count Top, Address 0x9B [7:0]; LB_LCM [7:0], Letterbox Line Count Mid, Address 0x9C [7:0]; LB_LCB [7:0], Letterbox Line Count Bottom, Address 0x9D [7:0]
- LB_TH [4:0], Letterbox Threshold Control, Address 0xDC [4:0]
- LB_SL [3:0], Letterbox Start Line, Address 0xDD [7:4]
- LB_EL [3:0], Letterbox End Line, Address 0xDD [3:0]
- IF Compensation Filter
- I2C Interrupt System
- Interrupt Request Output Operation
- INTRQ_DUR_SEL [1:0], Interrupt Duration Select, Address 0x40 [7:6], User Sub Map
- Interrupt Drive Level
- INTRQ_OP_SEL [1:0], Interrupt Duration Select, Address 0x40 [1:0], User Sub Map
- Multiple Interrupt Events
- Macrovision Interrupt Selection Bits
- MV_INTRQ_SEL [1:0], Macrovision Interrupt Selection Bits, Address 0x40 [5:4], User Sub Map
- PIXEL PORT CONFIGURATION
- MPU PORT DESCRIPTION
- I2C REGISTER MAPS
- PCB LAYOUT RECOMMENDATIONS
- TYPICAL CIRCUIT CONNECTION
- OUTLINE DIMENSIONS
ADV7188
Rev. A | Page 93 of 112
Bit
1
Address Register Bit Description 7 6 5 43210Comments Notes
0x69 Configuration 1 0 0 INSEL selects analog input muxing
01Composite—AIN11
1 0 S-video—Y on AIN10 and C on
AIN12
SDM_SEL [1:0]. Y/C and CVBS autodetect
mode select.
1 1 Composite/S-video autodetect
Composite on AIN11
Y on AIN11
C on AIN12
Reserved. 0 0 0 0 0 x
Reserved. 0 1 1 Reserved
0 Disables STDI functionality STDI_LINE_COUNT_MODE.
1 Enables STDI functionality
0x86 STDI Control
Reserved.
0 0 x 0
Reserved. 0 0 0 0 Set to default
0 0 0 LLC1 (nominally 27 MHz) selected
output on LLC1 pin
LLC_PAD_SEL [2:0]. These bits enable manual
selection of a clock for the LLC1 pin.
1 0 1 LLC2 (nominally 13.5 MHz)
selected output on LLC1 pin
For 16-bit 4:2:2 out, OF_SEL [3:0] = 0010.
0x8F Free-Run Line
Length 1
Reserved. 0 Set to default
0x99 CCAP1 (Read Only) CCAP1 [7:0]. Closed caption data bits. x x x x x x x x CCAP1 [7] contains parity bit for
Byte 0
Only for use with VBI System 2
0x9A CCAP2 (Read Only) CCAP2 [7:0]. Closed caption data bits. x x x x x x x x CCAP2 [7] contains parity bit for
Byte 0
Only for use with VBI System 2
0x9B Letterbox 1
(Read Only)
LB_LCT [7:0]. Letterbox data register. x x x x x x x x Reports the number of black lines
detected at the top of active video
0x9C Letterbox 2
(Read Only)
LB_LCM [7:0]. Letterbox data register. x x x x x x x x Reports the number of black
lines detected in the bottom
half of active video if subtitles
are detected
0x9D Letterbox 3
(Read Only)
LB_LCB [7:0]. Letterbox data register. x x x x x x x x Reports the number of black
lines detected at the bottom
of active video
This feature examines the active video
at the start and end of each field.,
enabling format detection even if
the video is not accompanied by a
CGMS or WSS sequence.
BL [13:8]. Block length data register. x x x x x x BL [13:0] reports the number of
clock cycles in a block of eight
lines of incoming video
Data is valid only if STDI_DVALID is 1 and
STDI_LINE_COUNT_MODE is set to 1.
Reserved x Reserved
0 Indicates that BL [13:0], LCF [10:0],
and LCVS [4:0] are not valid
parameters
0xB1 Standard Ident 1
(Read Only)
STDI_DVALID. Standard identification data
valid readback.
1 Indicates that BL [13:0], LCF [10:0],
and LCVS [4:0] are valid parameters
0xB2 Standard Ident 2
(Read Only)
BL [7:0]. Block length data register. x x x x x x x x BL [13:0] reports the number of
clock cycles in a block of eight
lines of incoming video
LCF [10:8]. Line count in field. x x x Reports the number of lines
between two vsyncs or one field
Data is valid only if STDI_DVALID is 1 and
STDI_LINE_COUNT_MODE is set to 1.
0xB3 Standard Ident 3
(Read Only)
LCVS [4:0]. x x x x x Reports the number of lines within
a vertical synchronization period
Data is valid only if STDI_DVALID is 1 and
STDI_LINE_COUNT_MODE is set to 1.
0xB4 Standard Ident 4
(Read Only)
LCF [7:0]. x x x x x x x x Data is valid only if STDI_DVALID is 1 and
STDI_LINE_COUNT_MODE is set to 1.
0xC3 ADC Switch 1 0000No connection
0001AIN1
0010AIN2
0011AIN3
0100AIN4
0101AIN5
0110AIN6
0111No connection
1000No connection
1001AIN7
1010AIN8
1011AIN9
1100AIN10
1101AIN11
1110AIN12
ADC0_SW [3:0]. Manual muxing control
for ADC0.
1111No connection
Set ADC_SW_MAN_EN to 1