Datasheet

ADV7188
Rev. A | Page 86 of 112
Bit
1
Address Register Bit Description 7 6 5 43210Comments Notes
0x0A Brightness Register BRI [7:0]. These bits control the brightness of
the video signal.
0 0 0 0 0 0 0 0 0x00 = 0 mV
0x7F = +204 mV
0x80 = −204 mV
0x0B Hue Register HUE [7:0]. These bits contain the value for the
color hue adjustment.
0 0 0 0 0 0 0 0 Hue range = −90° to +90°
0 Free-run mode dependent on
DEF_VAL_AUTO_EN
DEF_VAL_EN. Default value enable.
1Force free-run mode on and
output blue screen
0 Disable free-run mode DEF_VAL_AUTO_EN. Default value.
1 Enable automatic free-run mode
(blue screen)
When lock is lost, free-run mode can
be enabled to output stable timing,
clock, and a set color.
0x0C Default Value Y
DEF_Y [5:0]. Default value Y. These bits hold
the Y default value.
0 0 1 1 0 1 Y [7:0] = {DEF_Y [5:0], 0, 0} Default Y value output in free-run
mode.
0x0D Default Value C DEF_C [7:0]. Default value C. The Cr and Cb
default values are defined in these bits.
0 1 1 1 1 1 0 0 Cr [7:0] = {DEF_C [7:4], 0, 0, 0, 0}
Cb [7:0] = {DEF_C [3:0], 0, 0, 0, 0}
Default Cb/Cr value output in free-run
mode. Default values give blue screen
output.
Reserved. 0 0 0 0 0Set as default
0 Access user map SUB_USR_EN. This bit enables the user to
access the user sub map.
1 Access user sub map
See
Figure 48.
0x0E Analog Devices
Control
Reserved.
0 0 Set as default
Reserved. 0 Set to default
0 FB input operational FB_PWRDN.
1 FB input in power-saving mode
0 Chip power-down controlled by pin PDBP. Power-down bit priority. This bit selects
between the PWRDN bit and the
PWRDN
pin.
1 Bit has priority (pin disregarded)
This bit must be set to 1 for the PWRDN
bit to power down the part.
Reserved. 0 0 Set to default
0 System functional PWRDN. Power-down. This bit places the
decoder in full power-down mode.
1 Powered down
The PDBP bit must be set to 1 for the
PWRDN bit to power down the part
(see PDBP, 0x0F Bit 2).
Reserved. 0 Set to default
0 Normal operation
0x0F Power Management
RES. Chip Reset. This bit loads all I
2
C bits with
default values.
1 Start reset sequence
Executing reset takes approximately
2 ms. This bit is self-clearing.
IN_LOCK. x 1 = in lock (now)
LOST_LOCK. x 1 = lost lock (since last read)
FSC_LOCK. x 1 = F
SC
lock (now)
FOLLOW_PW. x 1 = peak white AGC mode active
Provides information about the
internal status of the decoder.
000 NTSM M/J
0 0 1 NTSC 443
010 PAL M
011 PAL 60
100 PAL B/G/H/I/D
101 SECAM
110 PAL Combination N
AD_RESULT [2:0]. Autodetection result. These
bits report the standard of the input video.
1 1 1 SECAM 525
Detected standard.
0x10 Status Register 1
(Read Only)
COL_KILL. x 1 = color kill is active Color kill.
0x11 IDENT (Read Only) IDENT [7:0]. These bits provide identification
on the revision of the part.
x x x x x x x x
MVCS DET. x MV color striping detected 1 = detected.
MVCS T3. x MV color striping type 0 = Type 2; 1 = Type 3.
MV_PS DET. x MV pseudosync detected 1 = detected.
MV_AGC DET. x MV AGC pulses detected 1 = detected.
LL_NSTD. x Nonstandard line length 1 = detected.
FSC_NSTD. x F
SC
frequency nonstandard 1 = detected.
0x12 Status Register 2
(Read Only)
Reserved. xx
0x13 INST_HLOCK. x 1 = horizontal lock achieved Unfiltered.
Status Register 3
(Read only)
GEMD. x 1 = Gemstar data detected When the GEMD bit goes high, it
remains high until the end of the
active video lines in that field.
SD_OP_50Hz. x SD field rate detect 0 = SD 60 Hz detected;
1 = SD 50 Hz detected.
CVBS. x Result of composite/S-video
autodetection
0 = Y/C; 1 = CVBS.