Datasheet

ADV7188
Rev. A | Page 79 of 112
PIXEL PORT CONFIGURATION
The ADV7188 has a very flexible pixel port that can be config-
ured in a variety of formats to accommodate downstream ICs.
Table 101 and Table 102 summarize the various functions that
the ADV7188 pins can have in different modes of operation.
The order of components, for example, the order of Cr and Cb,
on the output pixel bus can be changed. Refer to the
SWPC,
Swap Pixel Cr/Cb, Address 0x27 [7]
section. Table 101 indicates
the default positions for the Cr/Cb components.
PIXEL PORT–RELATED CONTROLS
OF_SEL [3:0], Output Format Selection, Address 0x03 [5:2]
The modes in which the ADV7188 pixel port can be configured
are controlled by OF_SEL [3:0]. See
Table 102 for details.
The default LLC frequency output on the LLC1 pin is approxi-
mately 27 MHz. For modes that operate with a nominal data
rate of 13.5 MHz (0001, 0010), the clock frequency on the
LLC1 pin stays at the higher rate of 27 MHz. For information
on outputting the nominal 13.5 MHz clock on the LLC1
pin, see the
LLC_PAD_SEL [2:0], LLC1 Output Selection,
Address 0x8F [6:4]
section.
SWPC, Swap Pixel Cr/Cb, Address 0x27 [7]
0 (default)—No swapping is allowed.
1—The Cr and Cb values can be swapped.
LLC_PAD_SEL [2:0], LLC1 Output Selection,
Address 0x8F [6:4]
The following I
2
C write allows the user to select between LLC1
(nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus
(16-/20-bit) output modes. See the
OF_SEL [3:0], Output Format
Selection, Address 0x03 [5:2]
section for additional information.
The LLC2 signal and data on the data bus are synchronized. By
default, the rising edge of LLC1/LLC2 is aligned with the Y data;
the falling edge occurs when the data bus holds C data. The polarity
of the clock, and therefore the Y/C assignments for the clock edges,
can be altered by using the polarity LLC pin.
000 (default)—The output is nominally 27 MHz LLC on the
LLC1 pin.
101—The output is nominally 13.5 MHz LLC on the LLC1 pin.
Table 101. P19 to P0 Output/Input Pin Mapping
Output of Data Port Pins P [19:0]
Processor, Format, and Mode
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Video Output, 8-Bit, 4:2:2 YCrCb [7:0]
Video Output, 10-Bit, 4:2:2 YCrCb [9:0]
Video Output, 16-Bit, 4:2:2 Y [7:0] CrCb [7:0]
Video Output, 20-Bit, 4:2:2 Y [9:0] CrCb [9:0]
Table 102. Standard Definition Pixel Port Modes
Pixel Port Pins P [19:0]
P [19:10] P9 [9:0]
OF_SEL [3:0] Format P [19:12] P [11:10] P [9:2] P [1:0]
0000 10-Bit at LLC1 4:2:2 YCrCb [9:2] YCrCb [1:0] Three-state Three-state
0001 20-Bit at LLC2 4:2:2 Y [9:2] Y [1:0] CrCb [9:2] CrCb [1:0]
0010 16-Bit at LLC2 4:2:2 Y [7:0] Three-state CrCb [7:0] Three-state
0011 (default) 8-Bit at LLC1 4:2:2 YCrCb [7:0] Three-state Three-state Three-state
0110 to 1111 Reserved Reserved—do not use