Datasheet

ADV7188
Rev. A | Page 7 of 112
THERMAL SPECIFICATIONS
Table 4.
Parameter Symbol Test Conditions Min Typ Max Unit
Junction-to-Case Thermal Resistance θ
JC
4-layer PCB with solid ground plane 7.6 °C/W
Junction-to-Ambient Thermal Resistance (Still Air) θ
JA
4-layer PCB with solid ground plane 38.1 °C/W
TIMING SPECIFICATIONS
A
VDD
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDDIO
= 3.0 V to 3.6 V, P
VDD
= 1.71 V to 1.89 V (operating temperature range, unless
otherwise noted).
Table 5.
Parameter
1, 2
Symbol Test Conditions Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency 28.63636 MHz
Frequency Stability ±50 ppm
I
2
C PORTT
3
SCLK Frequency 400 kHz
SCLK Minimum Pulse Width High t
1
0.6 μs
SCLK Minimum Pulse Width Low t
2
1.3 μs
Hold Time (Start Condition) t
3
0.6 μs
Setup Time (Start Condition) t
4
0.6 μs
SDA Setup Time t
5
100 ns
SCLK and SDA Rise Time t
6
300 ns
SCLK and SDA Fall Time t
7
300 ns
Setup Time for Stop Condition t
8
0.6 μs
RESET FEATURE
Reset Pulse Width 5 ms
CLOCK OUTPUTS
LLC1 Mark-Space Ratio t
9
:t
10
45:55 55:45 % duty cycle
LLC1 Rising to LLC2 Rising t
11
1 ns
LLC1 Rising to LLC2 Falling t
12
1 ns
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
4
t
13
Negative clock edge to start of valid data
(t
ACCESS
= t
10
− t
13
)
3.6 ns
Data Output Transitional Time
4
t
14
End of valid data to negative clock edge
(t
HOLD
= t
9
+ t
14
)
2.4 ns
Propagation Delay to Hi-Z t
15
6 ns
Max Output Enable Access Time t
16
7 ns
Min Output Enable Access Time t
17
4 ns
1
Temperature range T
MIN
to T
MAX
is −40°C to +85°C. The minimum/maximum specifications are guaranteed over this range.
2
Guaranteed by characterization.
3
TTL input values are 0 V to 3 V, with rise/fall times ≤3 ns, measured between the 10% and 90% points.
4
SDP timing figures obtained using default drive strength value (0xD5) in Register 0xF4.