Datasheet

ADV7188
Rev. A | Page 60 of 112
I
2
C INTERFACE
Dedicated I
2
C readback registers are available for CC, CGMS,
WSS, Gemstar, VPS, PDC/UTC, and VITC. Because teletext is a
high data rate standard, data extraction is supported only through
the ancillary data packet. The details of these registers and their
access procedures are described in this section.
User Interface for I
2
C Readback Registers
The VDP decodes all enabled VBI data standards in real time.
Because the I
2
C access speed is much slower than the decoded
rate, the registers may be updated with data from the next line
when they are being accessed. To avoid this, VDP has a self-
clearing CLEAR bit and an AVAILABLE status bit accompanying
all the I
2
C readback registers.
The user has to clear the I
2
C readback register by writing a high to
the CLEAR bit. This resets the state of the AVAILABLE bit to low
and indicates that the data in the associated readback registers is
not valid. After the VDP decodes the next line of the corresponding
VBI data, the decoded data is placed in the I
2
C readback register
and the AVAILABLE bit is set high to indicate that valid data is
now available.
Although the VDP, if present, decodes this VBI data in subsequent
lines, the decoded data is not updated to the readback registers
until the CLEAR bit is set high again. However, this data is available
through the 656 ancillary data packets.
The CLEAR and AVAILABLE bits are in the VDP_STATUS_CLEAR
(Address 0x78, user sub map, write only) and VDP_STATUS (0x78,
User Sub Map, read only) registers.
Example I
2
C Readback Procedure
To read one packet (line) of PDC data from the decoder
1.
Write 10 to I2C_GS_VPS_PDC_UTC [1:0] (Address 0x9C,
user sub map) to specify that PDC data has to be updated
to I
2
C registers.
2.
Write high to the GS_PDC_VPS_UTC_CLEAR bit
(Address 0x78, user sub map) to enable I
2
C register
updating.
3.
Poll the GS_PDC_VPS_UTC_AVL bit (Address 0x78,
user sub map) going high to check the availability of the
PDC packets.
4.
Read the data bytes from the PDC I
2
C registers. To read
another line or packet of data, repeat the previous steps.
To read a packet of CC, CGMS, or WSS data, only Steps 1 through
3 are required because these types of data have dedicated registers.
VDP—Content-Based Data Update
For certain standards, such as WSS, CGMS, Gemstar, PDC,
UTC, and VPS, the information content in the signal
transmitted remains the same over numerous lines, and the
user may want to be notified only when there is a change in the
information content or loss of the information content. The
user needs to enable content-based updating for the required
standard through the GS_VPS_PDC_UTC_CB_CHANGE and
WSS_CGMS_CB_CHANGE bits. Therefore, the AVAILABLE
bit shows the availability of that standard only when its content
has changed.
Content-based updating also applies to loss of data at the lines
where some data was previously present. Thus, for standards
like VPS, Gemstar, CGMS, and WSS, if no data arrives in the
next four lines programmed, the corresponding AVAILABLE bit
in the VDP_STATUS register is set high and the content in the
I
2
C registers for that standard is set to 0. The user must write
high to the corresponding CLEAR bit so that when a subsequent
valid line is decoded, the decoded results are available in the
I
2
C registers, with the AVAILABLE status bit set high.
If content-based updating is enabled, the AVAILABLE bit is set
high (assuming the CLEAR bit was written to) in the following
cases:
•
The data contents changed.
•
Data was being decoded and four lines with no data have
been detected.
• No data was being decoded and new data is now being
decoded.
GS_VPS_PDC_UTC_CB_CHANGE, Enable Content-
Based Updating for Gemstar/VPS/PDC/UTC,
Address 0x9C [5], User Sub Map
0—Disables content-based updating.
1 (default)—Enables content-based updating.
WSS_CGMS_CB_CHANGE, Enable Content-Based
Updating for WSS/CGMS, Address 0x9C [4], User Sub Map
0—Disables content-based updating.
1 (default)—Enables content-based updating.