Datasheet

ADV7188
Rev. A | Page 110 of 112
Use the following guidelines to ensure correct operation:
DIGITAL INPUTS
The digital inputs on the ADV7188 are designed to work with
3.3 V signals and are not tolerant of 5 V signals. Extra compo-
nents are needed if 5 V logic signals are required to be applied
to the decoder.
•
Use a crystal of the correct frequency, 28.63636 MHz.
Tolerance should be 50 ppm or better.
• User a parallel-resonant crystal.
•
Know the C
load
for the crystal part selected. The values of the
C1 and C2 capacitors must be calculated using this C
load
value.
XTAL AND LOAD CAPACITOR VALUES SELECTION
Figure 51 shows an example reference clock circuit for the
ADV7188. Special care must be taken when using a crystal
circuit to generate the reference clock for the ADV7188. Small
variations in reference clock frequency may cause autodetection
issues and impair the ADV7188 performance.
To find C1 and C2, use the following formula:
C = 2(C
load
− C
stray
) − C
pg
where C
stray
is usually 2 pF to 3 pF, depending on board traces,
and C
pg
(pin-to-ground capacitance) is 4 pF for the ADV7188.
C1 = 47pF C2 = 47pF
XTAL
28.63636MHz
05478-054
R = 1MΩ
For example, if C
load
is 30 pF, the values of C1 and C2 are
calculated to be 50 pF each, and the nearest standard capacitor
value is 47 pF.
Figure 51. Crystal Circuit