Datasheet

ADV7188
Rev. A | Page 11 of 112
Mnemonic Type Description Pin No.
68 SCLK I I
2
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
66 ALSB I
This pin selects the I
2
C address for the ADV7188. ALSB set to Logic 0 sets the address for
a write to 0x40; set to Logic 1 sets the address to 0x42.
64
RESET
I
System Reset Input (active low). A minimum low reset pulse width of 5 ms is required to reset the
ADV7188 circuitry.
27 LLC1 O
Line-Locked Clock 1. This is a line-locked output clock for the pixel data output by the ADV7188.
Nominally 27 MHz, but varies according to video line length.
26 LLC2 O
Line-Locked Clock 2. This is a divide-by-2 version of the LLC1 output clock for the pixel data
output by the ADV7188. Nominally 13.5 MHz, but varies according to video line length.
29 XTAL I
Crystal Input. This is the input pin for the 28.63636 MHz crystal, or it can be overdriven by an
external 3.3 V, 28.63636 MHz clock oscillator source. In crystal mode, the crystal must be a
fundamental crystal.
28 XTAL1 O
This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external
3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7188. In crystal mode, the
crystal must be a fundamental crystal.
36
PWRDN
I
Logic 0 on this pin places the ADV7188 in a power-down mode. Refer to the
I C Register Maps
2
section for more options on power-down modes for the ADV7188.
79
OE
I
When set to Logic 0,
OE enables the pixel output bus, P19 to P0 of the ADV7188. Logic 1 on the
OE pin places P19 to P0, HS, VS, and SFL into a high impedance state.
37 ELPF I The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 52.
12 SFL O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices, Inc., digital video
encoder.
63 SOY I
SYNC on Y. This input pin should only be used with the standard detection and identification function
(see the
Standard Detection and Identification section). This pin should be connected to the Y
signal of a component input for standard identification function.
51 REFOUT O
Internal Voltage Reference Output. Refer to
Figure 52 for a recommended capacitor network for
this pin.
52 CML O
Common-Mode Level. The CML pin is a common-mode level for the internal ADCs. Refer to
Figure 52 for a recommended capacitor network for this pin.
48, 49
CAPY1,
CAPY2
I ADC Capacitor Network. Refer to Figure 52 for a recommended capacitor network for this pin.
54, 55
CAPC1,
CAPC2
I ADC Capacitor Network. Refer to
Figure 52 for a recommended capacitor network for this pin.