Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- REVISION HISTORY
- INTRODUCTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- ANALOG FRONT END
- ANALOG INPUT MUXING
- MANUAL INPUT MUXING
- XTAL CLOCK INPUT PIN FUNCTIONALITY
- 28.63636 MHz CRYSTAL OPERATION
- ANTIALIASING FILTERS
- SCART AND FAST BLANKING
- FAST BLANK CONTROL
- FB_MODE [1:0], Address 0xED [1:0]
- Static Mux Selection Control
- Alpha Blend Coefficient
- Fast Blank Edge Shaping
- Contrast Reduction
- Contrast Reduction Enable
- Contrast Mode
- Fast Blank and Contrast Reduction Programmable Thresholds
- FB_INV, Address 0xED [3], Write Only
- Readback of FB Pin Status
- FB Timing
- Alignment of FB Signal
- Color Space Converter Manual Adjust
- GLOBAL CONTROL REGISTERS
- STANDARD DEFINITION PROCESSOR (SDP)
- SD LUMA PATH
- SD CHROMA PATH
- SYNC PROCESSING
- VBI DATA RECOVERY
- GENERAL SETUP
- Video Standard Selection
- Autodetection of SD Modes
- VID_SEL [3:0], Address 0x00 [7:4]
- AD_SEC525_EN, SECAM 525 Autodetect Enable, Address 0x07 [7]
- AD_SECAM_EN, SECAM Autodetect Enable, Address 0x07 [6]
- AD_N443_EN, NTSC 443 Autodetect Enable, Address 0x07 [5]
- AD_P60_EN, PAL 60 Autodetect Enable, Address 0x07 [4]
- AD_PALN_EN, PAL N Autodetect Enable, Address 0x07 [3]
- AD_PALM_EN, PAL M Autodetect Enable, Address 0x07 [2]
- AD_NTSC_EN, NTSC Autodetect Enable, Address 0x07 [1]
- AD_PAL_EN, PAL (B/G/I/H) Autodetect Enable, Address 0x07 [0]
- Subcarrier Frequency Lock Inversion
- Lock-Related Controls
- VS_COAST_MODE [1:0], Address 0xF9 [3:2]
- ST_NOISE_VLD, Sync Tip Noise Measurement Valid, Address 0xDE [3], Read Only
- ST_NOISE [10:0], Sync Tip Noise Measurement, Addresses 0xDE [2:0], 0xDF [7:0]
- COLOR CONTROLS
- CON [7:0], Contrast Adjust, Address 0x08 [7:0]
- SD_SAT_CB [7:0], SD Saturation Cb Channel, Address 0xE3 [7:0]
- SD_SAT_CR [7:0], SD Saturation Cr Channel, Address 0xE4 [7:0]
- SD_OFF_CB [7:0], SD Offset Cb Channel, Address 0xE1 [7:0]
- SD_OFF_CR [7:0], SD Offset Cr Channel, Address 0xE2 [7:0]
- BRI [7:0], Brightness Adjust, Address 0x0A [7:0]
- HUE [7:0], Hue Adjust, Address 0x0B [7:0]
- DEF_Y [5:0], Default Value Y, Address 0x0C [7:2]
- DEF_C [7:0], Default Value C, Address 0x0D [7:0]
- DEF_VAL_EN, Default Value Enable, Address 0x0C [0]
- DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1]
- CLAMP OPERATION
- LUMA FILTER
- CHROMA FILTER
- GAIN OPERATION
- Luma Gain
- Chroma Gain
- CAGC [1:0], Chroma Automatic Gain Control, Address 0x2C [1:0]
- CAGT [1:0], Chroma Automatic Gain Timing, Address 0x2D [7:6]
- CMG [11:0]/CG [11:0], Chroma Manual Gain/Chroma Gain, Address 0x2D [3:0], Address 0x2E [7:0]
- CKE, Color-Kill Enable, Address 0x2B [6]
- CKILLTHR [2:0], Color-Kill Threshold, Address 0x3D [6:4]
- CHROMA TRANSIENT IMPROVEMENT (CTI)
- DIGITAL NOISE REDUCTION (DNR) AND LUMA PEAKING FILTER
- COMB FILTERS
- NTSC Comb Filter Settings
- PAL Comb Filter Settings
- Vertical Blank Control
- NVBIOLCM [1:0], NTSC VBI Odd Field Luma Comb Mode, Address 0xEB [7:6]
- NVBIELCM [1:0], NTSC VBI Even Field Luma Comb Mode, Address 0xEB [5:4]
- PVBIOLCM [1:0], PAL VBI Odd Field Luma Comb Mode, Address 0xEB [3:2]
- PVBIELCM [1:0], PAL VBI Even Field Luma Comb Mode, Address 0xEB [1:0]
- NVBIOCCM [1:0], NTSC VBI Odd Field Chroma Comb Mode, Address 0xEC [7:6]
- NVBIECCM [1:0], NTSC VBI Even Field Chroma Comb Mode, Address 0xEC [5:4]
- PVBIOCCM [1:0], PAL VBI Odd Field Chroma Comb Mode, Address 0xEC [3:2]
- PVBIECCM [1:0], PAL VBI Even Field Chroma Comb Mode, Address 0xEC [1:0]
- AV CODE INSERTION AND CONTROLS
- BT656-4, ITU-R BT.656-4 Enable, Address 0x04 [7]
- SD_DUP_AV, Duplicate AV Codes, Address 0x03 [0]
- VBI_EN, Vertical Blanking Interval Data Enable, Address 0x03 [7]
- BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2]
- RANGE, Range Selection, Address 0x04 [0]
- AUTO_PDC_EN, Automatic Programmed Delay Control, Address 0x27 [6]
- LTA [1:0], Luma Timing Adjust, Address 0x27 [1:0]
- CTA [2:0], Chroma Timing Adjust, Address 0x27 [5:3]
- SYNCHRONIZATION OUTPUT SIGNALS
- HS Configuration
- VS and FIELD Configuration
- NEWAVMODE, New AV Mode, Address 0x31 [4]
- HVSTIM, Horizontal VS Timing, Address 0x31 [3]
- VSBHO, VS Begin Horizontal Position Odd, Address 0x32 [7]
- VSBHE, VS Begin Horizontal Position Even, Address 0x32 [6]
- VSEHO VS, End Horizontal Position Odd, Address 0x33 [7]
- VSEHE, VS End Horizontal Position Even, Address 0x33 [6]
- PVS, Polarity VS, Address 0x37 [5]
- PF, Polarity FIELD, Address 0x37 [3]
- NVBEGDELO, NTSC Vsync Begin Delay on Odd Field, Address 0xE5 [7]
- NVBEGDELE, NTSC Vsync Begin Delay on Even Field, Address 0xE5 [6]
- NVBEGSIGN, NTSC Vsync Begin Sign, Address 0xE5 [5]
- NVBEG [4:0], NTSC Vsync Begin, Address 0xE5 [4:0]
- NVENDDELO, NTSC Vsync End Delay on Odd Field, Address 0xE6 [7]
- NVENDDELE, NTSC Vsync End Delay on Even Field, Address 0xE6 [6]
- NVENDSIGN, NTSC Vsync End Sign, Address 0xE6 [5]
- NVEND [4:0], NTSC Vsync End, Address 0xE6 [4:0]
- NFTOGDELO, NTSC Field Toggle Delay on Odd Field, Address 0xE7 [7]
- NFTOGDELE, NTSC Field Toggle Delay on Even Field, Address 0xE7 [6]
- NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]
- NFTOG [4:0], NTSC Field Toggle, Address 0xE7 [4:0]
- PVBEGDELO, PAL Vsync Begin Delay on Odd Field, Address 0xE8 [7]
- PVBEGDELE, PAL Vsync Begin Delay on Even Field, Address 0xE8 [6]
- PVBEGSIGN, PAL Vsync Begin Sign, Address 0xE8 [5]
- PVBEG [4:0], PAL Vsync Begin, Address 0xE8 [4:0]
- PVENDDELO, PAL Vsync End Delay on Odd Field, Address 0xE9 [7]
- PVENDDELE, PAL Vsync End Delay on Even Field, Address 0xE9 [6]
- PVENDSIGN, PAL Vsync End Sign, Address 0xE9 [5]
- PVEND [4:0], PAL Vsync End, Address 0xE9 [4:0]
- PFTOGDELO, PAL Field Toggle Delay on Odd Field, Address 0xEA [7]
- PFTOGDELE, PAL Field Toggle Delay on Even Field, Address 0xEA [6]
- PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]
- PFTOG, PAL Field Toggle, Address 0xEA [4:0]
- SYNC PROCESSING
- VBI DATA DECODE
- VDP Default Configuration
- VDP Manual Configuration
- MAN_LINE_PGM, Enable Manual Line Programming of VBI Standards, Address 0x64 [7], User Sub Map
- VBI_DATA_Px_Ny [3:0], VBI Standard to be Decoded on Line x for PAL, Line y for NTSC, Addresses 0x64 to 0x77, User Sub Map
- VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual Selection of Teletext Type, Address 0x60 [2], User Sub Map
- VDP_TTXT_TYPE_MAN [1:0], Specify the Teletext Type, Address 0x60 [1:0], User Sub Map
- VDP Ancillary Data Output
- ADF_ENABLE, Enable Ancillary Data Output Through 656 Stream, Address 0x62 [7], User Sub Map
- ADF_DID [4:0], User-Specified Data ID Word in Ancillary Data, Address 0x62 [4:0], User Sub Map
- ADF_SDID [5:0], User-Specified Secondary Data ID Word in Ancillary Data, Address 0x63 [5:0], User Sub Map
- DUPLICATE_ADF, Enable Duplication/Spreading of Ancillary Data over Y and C Buses, Address 0x63 [7], User Sub Map
- ADF_MODE [1:0], Determine the Ancillary Data Output Mode, Address 0x62 [6:5], User Sub Map
- Structure of VBI Words in Ancillary Data Stream
- VDP Framing Code
- I2C INTERFACE
- STANDARD DETECTION AND IDENTIFICATION
- Notes
- STDI_DVALID, Standard Identification Data Valid Read Back, Address 0xB1 [7]
- STDI_LINE_COUNT_MODE, Address 0x86 [3]
- BL [13:0], Block Length Readback, Address 0xB1 [5:0], Address 0xB2 [7:0]
- LCVS [4:0], Line Count in Vsync Readback, Address 0xB3 [7:3]
- LCF [10:0], Line Count in Field Readback, Address 0xB3 [2:0], Address 0xB4 [7:0]
- FCL [12:0], 1/256th of Field Length in Number of Crystal Clocks Read back, Address 0xCA [4:0], Address 0xCB [7:0]
- STDI Readback Values for SD, PR, and HD
- I2C READBACK REGISTERS
- Teletext
- CGMS and WSS
- CC
- CC_CLEAR, Closed Captioning Clear, Address 0x78 [0], User Sub Map, Write Only, Self-Clearing
- CC_AVL, Closed Captioning Available, Address 0x78 [0], User Sub Map, Read Only
- CC_EVEN_FIELD, Address 0x78 [1], User Sub Map, Read Only
- VDP_CCAP_DATA_0, Address 0x79 [7:0], User Sub Map, Read Only
- VDP_CCAP_DATA_1, Address 0x7A [7:0], User Sub Map, Read Only
- VITC
- VPS/PDC/UTC/Gemstar
- I2C_GS_VPS_PDC_UTC (VDP) [1:0], Address 0x9C [6:5], User Sub Map
- GS_PDC_VPS_UTC_CLEAR, GS/PDC/VPS/UTC Clear, Address 0x78 [4], User Sub Map, Write Only, Self-Clearing
- GS_PDC_VPS_UTC_AVL, GS/PDC/VPS/UTC Available, Address 0x78 [4], User Sub Map, Read Only
- VDP_GS_VPS_PDC_UTC Readback Registers, Addresses 0x84 to 0x90, User Sub Map
- VPS
- Gemstar
- AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map
- GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only
- PDC/UTC
- VBI System 2
- Gemstar Data Recovery
- GDE_SEL_OLD_ADF, Address 0x4C [3], User Map
- Gemstar Bit Names
- Gemstar 2× Format, Half-Byte Output Mode
- Gemstar 1× Format, Half-Byte Output Mode
- NTSC CC Data
- PAL CC Data
- GDECEL [15:0], Gemstar Decoding Even Lines, Address 0x48 [7:0], Address 0x49 [7:0]
- GDECOL [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0]
- GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0]
- Letterbox Detection
- Detection at the Start of a Field
- Detection at the End of a Field
- Detection at the Midrange
- LB_LCT [7:0], Letterbox Line Count Top, Address 0x9B [7:0]; LB_LCM [7:0], Letterbox Line Count Mid, Address 0x9C [7:0]; LB_LCB [7:0], Letterbox Line Count Bottom, Address 0x9D [7:0]
- LB_TH [4:0], Letterbox Threshold Control, Address 0xDC [4:0]
- LB_SL [3:0], Letterbox Start Line, Address 0xDD [7:4]
- LB_EL [3:0], Letterbox End Line, Address 0xDD [3:0]
- IF Compensation Filter
- I2C Interrupt System
- Interrupt Request Output Operation
- INTRQ_DUR_SEL [1:0], Interrupt Duration Select, Address 0x40 [7:6], User Sub Map
- Interrupt Drive Level
- INTRQ_OP_SEL [1:0], Interrupt Duration Select, Address 0x40 [1:0], User Sub Map
- Multiple Interrupt Events
- Macrovision Interrupt Selection Bits
- MV_INTRQ_SEL [1:0], Macrovision Interrupt Selection Bits, Address 0x40 [5:4], User Sub Map
- PIXEL PORT CONFIGURATION
- MPU PORT DESCRIPTION
- I2C REGISTER MAPS
- PCB LAYOUT RECOMMENDATIONS
- TYPICAL CIRCUIT CONNECTION
- OUTLINE DIMENSIONS
ADV7188
Rev. A | Page 100 of 112
Address
Dec Hex Register Name RW 7 6 5 4 3 2 1 0
Reset
Value
(Hex)
116 74 VDP_LINE_01E RW VBI_DATA_
P21_N19.3
VBI_DATA_P21_
N19.2
VBI_DATA_P21_
N19.1
VBI_DATA_P21_
N19.0
VBI_DATA_P334_
N282.3
VBI_DATA_P334_
N282.2
VBI_DATA_P334_
N282.1
VBI_DATA_
P334_N282.0
00000000 00
117 75 VDP_LINE_01F RW VBI_DATA_
P22_N20.3
VBI_DATA_P22_
N20.2
VBI_DATA_P22_
N20.1
VBI_DATA_P22_
N20.0
VBI_DATA_P335_
N283.3
VBI_DATA_P335_
N283.2
VBI_DATA_P335_
N283.1
VBI_DATA_
P335_N283.0
00000000 00
118 76 VDP_LINE_020 RW VBI_DATA_
P23_N21.3
VBI_DATA_P23_
N21.2
VBI_DATA_P23_
N21.1
VBI_DATA_P23_
N21.0
VBI_DATA_P336_
N284.3
VBI_DATA_P336_
N284.2
VBI_DATA_P336_
N284.1
VBI_DATA_
P336_N284.0
00000000 00
119 77 VDP_LINE_021 RW VBI_DATA_
P24_N22.3
VBI_DATA_P24_
N22.2
VBI_DATA_P24_
N22.1
VBI_DATA_P24_
N22.0
VBI_DATA_P337_
N285.3
VBI_DATA_P337_
N285.2
VBI_DATA_P337_
N285.1
VBI_DATA_
P337_N285.0
00000000 00
120 78 VDP_STATUS_
CLEAR
W VITC_CLEAR GS_PDC_VPS_
UTC_CLEAR
CGMS_WSS_
CLEAR
CC_CLEAR 00000000 00
120 78 VDP_STATUS R TTXT_AVL VITC_AVL GS_DATA_TYPE GS_PDC_VPS_
UTC_AVL
CGMS_WSS_AVL CC_EVEN_FIELD CC_AVL – –
121 79 VDP_CCAP_
DATA_0
R CCAP_BYTE_1.7 CCAP_BYTE_1.6 CCAP_BYTE_1.5 CCAP_BYTE_1.4 CCAP_BYTE_1.3 CCAP_BYTE_1.2 CCAP_BYTE_1.1 CCAP_
BYTE_1.0
– –
122 7A VDP_CCAP_
DATA_1
R CCAP_BYTE_2.7 CCAP_BYTE_2.6 CCAP_BYTE_2.5 CCAP_BYTE_2.4 CCAP_BYTE_2.3 CCAP_BYTE_2.2 CCAP_BYTE_2.1 CCAP_
BYTE_2.0
– –
125 7D CGMS_WSS_
DATA_0
R zero zero zero zero CGMS_CRC.5 CGMS_CRC.4 CGMS_CRC.3 CGMS_
CRC.2
– –
126 7E CGMS_WSS_
DATA_1
R CGMS_CRC.1 CGMS_CRC.0 CGMS_WSS.13 CGMS_WSS.12 CGMS_WSS.11 CGMS_WSS.10 CGMS_WSS.9 CGMS_
WSS.8
– –
127 7F CGMS_WSS_
DATA_2
R CGMS_WSS.7 CGMS_WSS.6 CGMS_WSS.5 CGMS_WSS.4 CGMS_WSS.3 CGMS_WSS.2 CGMS_WSS.1 CGMS_
WSS.0
– –
132 84 VDP_GS_VPS_
PDC_UTC_0
R GS_VPS_PDC_
UTC_BYTE_0.7
GS_VPS_PDC_
UTC_BYTE_0.6
GS_VPS_PDC_
UTC_BYTE_0.5
GS_VPS_PDC_
UTC_BYTE_0.4
GS_VPS_PDC_
UTC_BYTE_0.3
GS_VPS_PDC_
UTC_BYTE_0.2
GS_VPS_PDC_
UTC_BYTE_0.1
GS_VPS_PDC_
UTC_BYTE_0.0
– –
133 85 VDP_GS_VPS_
PDC_UTC_1
R GS_VPS_PDC_
UTC_BYTE_1.7
GS_VPS_PDC_
UTC_BYTE_1.6
GS_VPS_PDC_
UTC_BYTE_1.5
GS_VPS_PDC_
UTC_BYTE_1.4
GS_VPS_PDC_
UTC_BYTE_1.3
GS_VPS_PDC_
UTC_BYTE_1.2
GS_VPS_PDC_
UTC_BYTE_1.1
GS_VPS_PDC_
UTC_BYTE_1.0
– –
134 86 VDP_GS_VPS_
PDC_UTC_2
R GS_VPS_PDC_
UTC_BYTE_2.7
GS_VPS_PDC_
UTC_BYTE_2.6
GS_VPS_PDC_
UTC_BYTE_2.5
GS_VPS_PDC_
UTC_BYTE_2.4
GS_VPS_PDC_
UTC_BYTE_2.3
GS_VPS_PDC_
UTC_BYTE_2.2
GS_VPS_PDC_
UTC_BYTE_2.1
GS_VPS_PDC_
UTC_BYTE_2.0
– –
135 87 VDP_GS_VPS_
PDC_UTC_3
R GS_VPS_PDC_
UTC_BYTE_3.7
GS_VPS_PDC_
UTC_BYTE_3.6
GS_VPS_PDC_
UTC_BYTE_3.5
GS_VPS_PDC_
UTC_BYTE_3.4
GS_VPS_PDC_
UTC_BYTE_3.3
GS_VPS_PDC_
UTC_BYTE_3.2
GS_VPS_PDC_
UTC_BYTE_3.1
GS_VPS_PDC_
UTC_BYTE_3.0
– –
136 88 VDP_VPS_PDC_
UTC_4
R VPS_PDC_UTC_
BYTE_4.7
VPS_PDC_UTC_
BYTE_4.6
VPS_PDC_UTC_
BYTE_4.5
VPS_PDC_UTC_
BYTE_4.4
VPS_PDC_UTC_
BYTE_4.3
VPS_PDC_UTC_
BYTE_4.2
VPS_PDC_UTC_
BYTE_4.1
VPS_PDC_
UTC_BYTE_4.0
– –
137 89 VDP_VPS_PDC_
UTC_5
R VPS_PDC_UTC_
BYTE_5.7
VPS_PDC_UTC_
BYTE_5.6
VPS_PDC_UTC_
BYTE_5.5
VPS_PDC_UTC_
BYTE_5.4
VPS_PDC_UTC_
BYTE_5.3
VPS_PDC_UTC_
BYTE_5.2
VPS_PDC_UTC_
BYTE_5.1
VPS_PDC_
UTC_BYTE_5.0
– –
138 8A VDP_VPS_PDC_
UTC_6
R VPS_PDC_UTC_
BYTE_6.7
VPS_PDC_UTC_
BYTE_6.6
VPS_PDC_UTC_
BYTE_6.5
VPS_PDC_UTC_
BYTE_6.4
VPS_PDC_UTC_
BYTE_6.3
VPS_PDC_UTC_
BYTE_6.2
VPS_PDC_UTC_
BYTE_6.1
VPS_PDC_
UTC_BYTE_6.0
– –
139 8B VDP_VPS_PDC_
UTC_7
R VPS_PDC_UTC_
BYTE_7.7
VPS_PDC_UTC_
BYTE_7.6
VPS_PDC_UTC_
BYTE_7.5
VPS_PDC_UTC_
BYTE_7.4
VPS_PDC_UTC_
BYTE_7.3
VPS_PDC_UTC_
BYTE_7.2
VPS_PDC_UTC_
BYTE_7.1
VPS_PDC_
UTC_BYTE_7.0
– –
140 8C VDP_VPS_PDC_
UTC_8
R VPS_PDC_UTC_
BYTE_8.7
VPS_PDC_UTC_
BYTE_8.6
VPS_PDC_UTC_
BYTE_8.5
VPS_PDC_UTC_
BYTE_8.4
VPS_PDC_UTC_
BYTE_8.3
VPS_PDC_UTC_
BYTE_8.2
VPS_PDC_UTC_
BYTE_8.1
VPS_PDC_
UTC_BYTE_8.0
– –
141 8D VDP_VPS_PDC_
UTC_9
R VPS_PDC_UTC_
BYTE_9.7
VPS_PDC_UTC_
BYTE_9.6
VPS_PDC_UTC_
BYTE_9.5
VPS_PDC_UTC_
BYTE_9.4
VPS_PDC_UTC_
BYTE_9.3
VPS_PDC_UTC_
BYTE_9.2
VPS_PDC_UTC_
BYTE_9.1
VPS_PDC_
UTC_BYTE_9.0
– –
142 8E VDP_VPS_PDC_
UTC_10
R VPS_PDC_UTC_
BYTE_10.7
VPS_PDC_UTC_
BYTE_10.6
VPS_PDC_UTC_
BYTE_10.5
VPS_PDC_UTC_
BYTE_10.4
VPS_PDC_UTC_
BYTE_10.3
VPS_PDC_UTC_
BYTE_10.2
VPS_PDC_UTC_
BYTE_10.1
VPS_PDC_
UTC_BYTE_10.0
– –
143 8F VDP_VPS_PDC_
UTC_11
R VPS_PDC_UTC_
BYTE_11.7
VPS_PDC_UTC_
BYTE_11.6
VPS_PDC_UTC_
BYTE_11.5
VPS_PDC_UTC_
BYTE_11.4
VPS_PDC_UTC_
BYTE_11.3
VPS_PDC_UTC_
BYTE_11.2
VPS_PDC_UTC_
BYTE_11.1
VPS_PDC_
UTC_BYTE_11.0
– –
144 90 VDP_VPS_PDC_
UTC_12
R VPS_PDC_UTC_
BYTE_12.7
VPS_PDC_UTC_
BYTE_12.6
VPS_PDC_UTC_
BYTE_12.5
VPS_PDC_UTC_
BYTE_12.4
VPS_PDC_UTC_
BYTE_12.3
VPS_PDC_UTC_
BYTE_12.2
VPS_PDC_UTC_
BYTE_12.1
VPS_PDC_
UTC_BYTE_12.0
– –
146 92 VDP_VITC_
DATA_0
R VITC_DATA_1.7 VITC_DATA_1.6 VITC_DATA_1.5 VITC_DATA_1.4 VITC_DATA_1.3 VITC_DATA_1.2 VITC_DATA_1.1 VITC_DATA_1.0 – –
147 93 VDP_VITC_
DATA_1
R VITC_DATA_2.7 VITC_DATA_2.6 VITC_DATA_2.5 VITC_DATA_2.4 VITC_DATA_2.3 VITC_DATA_2.2 VITC_DATA_2.1 VITC_DATA_2.0 – –
148 94 VDP_VITC_
DATA_2
R VITC_DATA_3.7 VITC_DATA_3.6 VITC_DATA_3.5 VITC_DATA_3.4 VITC_DATA_3.3 VITC_DATA_3.2 VITC_DATA_3.1 VITC_DATA_3.0 – –
149 95 VDP_VITC_
DATA_3
R VITC_DATA_4.7 VITC_DATA_4.6 VITC_DATA_4.5 VITC_DATA_4.4 VITC_DATA_4.3 VITC_DATA_4.2 VITC_DATA_4.1 VITC_DATA_4.0 – –
150 96 VDP_VITC_
DATA_4
R VITC_DATA_5.7 VITC_DATA_5.6 VITC_DATA_5.5 VITC_DATA_5.4 VITC_DATA_5.3 VITC_DATA_5.2 VITC_DATA_5.1 VITC_DATA_5.0 – –
151 97 VDP_VITC_
DATA_5
R VITC_DATA_6.7 VITC_DATA_6.6 VITC_DATA_6.5 VITC_DATA_6.4 VITC_DATA_6.3 VITC_DATA_6.2 VITC_DATA_6.1 VITC_DATA_6.0 – –
152 98 VDP_VITC_
DATA_6
R VITC_DATA_7.7 VITC_DATA_7.6 VITC_DATA_7.5 VITC_DATA_7.4 VITC_DATA_7.3 VITC_DATA_7.2 VITC_DATA_7.1 VITC_DATA_7.0 – –
153 99 VDP_VITC_
DATA_7
R VITC_DATA_8.7 VITC_DATA_8.6 VITC_DATA_8.5 VITC_DATA_8.4 VITC_DATA_8.3 VITC_DATA_8.2 VITC_DATA_8.1 VITC_DATA_8.0 – –
154 9A VDP_VITC_
DATA_8
R VITC_DATA_9.7 VITC_DATA_9.6 VITC_DATA_9.5 VITC_DATA_9.4 VITC_DATA_9.3 VITC_DATA_9.2 VITC_DATA_9.1 VITC_DATA_9.0 – –
155 9B VDP_VITC_
CALC_CRC
R VITC_CRC.7 VITC_CRC.6 VITC_CRC.5 VITC_CRC.4 VITC_CRC.3 VITC_CRC.2 VITC_CRC.1 VITC_CRC.0 – –
156 9C VDP_
OUTPUT_SEL
RW I2C_GS_VPS_
PDC_UTC.1
I2C_GS_VPS_
PDC_UTC.0
GS_VPS_PDC_
UTC_CB_
CHANGE
WSS_CGMS_
CB_CHANGE
00110000 30