Datasheet

ADV7184
Rev. A | Page 62 of 112
VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F [2],
User Sub Map
1—Clears the VDP_CGMS_WSS_CHNGD_Q bit.
VDP_GS_VPS_PDC_UTC_CHNG_CLR,
Address 0x4F [4], User Sub Map
1—Clears the VDP_GS_VPS_PDC_UTC_CHNG_Q bit.
VDP_VITC_CLR, Address 0x4F [6], User Sub Map
1—Clears the VDP_VITC_Q bit.
STANDARD DETECTION AND IDENTIFICATION
The standard detection and identification (STDI) block of the
ADV7184 monitors the synchronization signals received on the
SOY pin. STDI_LINE_COUNT_MODE must be set to 1 to enable
the STDI block and achieve valid synchronization signal analysis.
Four key measurements are performed:
•
Block Length BL [13:0]. This is the number of clock cycles in
a block of eight lines. From this, the time duration of one line
can be concluded. Note that the crystal frequency determines
the clock cycle and that a crystal frequency of 28.63636 MHz
should be used for the ADV7184.
•
Line Count in Field LCF [10:0]. The LCF [10:0] readback
value is the number of lines between two vsyncs, that is,
over one field.
•
Line Count in Vsync LCVS [4:0]. The LCVS [4:0] readback
value is the number of lines within one vsync period.
• Field Length FCL [12:0]. This is the number of clock cycles
in 1/256
th
of a field. Multiplying this value by 256 calculates
the field length in clock cycles.
By interpreting these four parameters, it is possible to
distinguish among the types of input signals.
A data valid flag, STDI_VALID, is provided that is held low
during the measurements. The four parameters should only be
read after the STDI_VALID flag has gone high. Refer to
Table 76
for information on the readback values.
Notes
• Types of synchronization pulses include horizontal
synchronization pulses, equalization and serration
pulses, and Macrovision pulses.
•
Macrovision pseudosynchronization and AGC pulses are
counted by the STDI block in normal readback mode. This
does not prohibit the identification of the video signal.
• The ADV7184 only measures the parameters; it does not take
any action based on these measurements. Therefore, the part
helps to identify the input to avoid problems in the scheduling
of a system controller, but it does not reconfigure itself.
STDI_DVALID, Standard Identification Data Valid Read
Back, Address 0xB1 [7]
X—This bit is set by the ADV7184 as soon as the measurements
of the STDI block are finished. A high level signals the validity
of the BL, LCVS, LCF, and STDI_INTLCD parameters. To
prevent false readouts, especially during the signal acquisition,
the DVALID bit only goes high after recording four fields with
the same length. As a result, the measurements can require up
to five fields to finish.
STDI_LINE_COUNT_MODE, Address 0x86 [3]
0 (default)—Disables the STDI functionality.
1—Enables STDI functionality. This enables valid readback of
the STDI block registers.
BL [13:0], Block Length Readback, Address 0xB1 [5:0],
Address 0xB2 [7:0]
XX XXXX XXXX XXXX—Number of clock cycles in a block of
eight lines of incoming video. Data is only valid if STDI_DVALID
is high.
LCVS [4:0], Line Count in Vsync Readback,
Address 0xB3 [7:3]
X XXXX—Number of lines within a vertical synchronization
period. Data is only valid if STDI_DVALID is high.
LCF [10:0], Line Count in Field Readback,
Address 0xB3 [2:0], Address 0xB4 [7:0]
XX XXXX XXXX—Number of lines between two vsyncs per
one field/frame. Data is only valid if STDI_DVALID is high.
FCL [12:0], 1/256
th
of Field Length in Number of Crystal
Clocks Read back, Address 0xCA [4:0], Address 0xCB [7:0]
XXX—Number of crystal clocks (with the recommended
28.63636 MHz frequency) in 1/256
th
of a field. Data is only valid
if STDI_DVALID is high.