Datasheet

ADV7184
Rev. A | Page 10 of 112
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
HS
3
DGND
4
DVDDIO
7
P9
6
P10
5
P11
1
VS
8
P8
9
DGND
10
DVDD
12
SFL
13
TEST2
14
DGND
15
DVDDIO
16
TEST8
17
TEST12
18
TEST11
19
P7
20
P6
11
INT
59
58
57
54
55
56
60
53
52
AIN11
AIN4
AIN10
CAPC1
CAPC2
AGND
AIN5
AGND
CML
51
REFOUT
49
CAPY2
48
CAPY1
47
AGND
46
AIN3
45
AIN9
44
AIN2
43
AIN8
42
AIN1
41
AIN7
50
AVDD
21
P5
22
P4
23
P3
24
P2
25
TEST3
26
LLC2
27
LLC1
28
XTAL1
29
XTAL
30
DVDD
31
DGND
32
P1
33
P0
34
TEST10
35
TEST9
36
PWRDN
37
ELPF
38
PVDD
39
AGND
40
FB
80
FIELD
79
OE
78
TEST1
77
TEST6
76
P12
75
P13
74
P14
73
P15
72
DVDD
71
DGND
70
TEST0
69
TEST4
68
SCLK
67
SDA
66
ALSB
65
TEST7
64
RESET
63
SOY
62
AIN6
61
AIN12
PIN 1
ADV7184
TOP VIEW
(Not to Scale)
05479-005
Figure 5. 80-Lead LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type Description
3, 9, 14, 31, 71 DGND G Digital Ground.
39, 47, 53, 56 AGND G Analog Ground.
4, 15 DVDDIO P Digital I/O Supply Voltage (3.3 V).
10, 30, 72 DVDD P Digital Core Supply Voltage (1.8 V).
50 AVDD P Analog Supply Voltage (3.3 V).
38 PVDD P PLL Supply Voltage (1.8 V).
42, 44, 46, 58,
60, 62, 41, 43,
45, 57, 59, 61
AIN1 to
AIN12
I Analog Video Input Channels.
11
INT
O
Interrupt Request Output. An interrupt occurs when certain signals are detected on the input
video. See the User Sub Map register details in
Table 107.
40 FB I
Fast Blank. FB is a fast switch overlay input that switches between CVBS and RGB
analog input signals.
70, 78, 13, 25, 69,
35, 34, 18, 17
TEST0 to
TEST4,
TEST9 to
TEST12
Leave these pins unconnected.
77, 65
TEST6,
TEST7
Tie to AGND.
16 TEST8 Tie to DVDDIO.
33, 32, 24 to 19,
8 to 5, 76 to 73
P0 to P15 O Video Pixel Output Ports.
2 HS O Horizontal Synchronization Output Signal.
1 VS O Vertical Synchronization Output Signal.
80 FIELD O Field Synchronization Output Signal.