Datasheet

Data Sheet ADV7181C
Rev. E | Page 7 of 20
Timing Diagrams
07513-103
SDATA
SCLK
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
Figure 2. I
2
C Timing
0
7513-104
LLC
P0 TO P19, VS, HS,
FIELD/DE,
SFL/SYNC_OUT
t
9
t
10
t
12
t
11
Figure 3. Pixel Port and Control SDR Output Timing (SD Core)
07513-105
t
9
LLC
P0 TO P19
t
13
t
14
t
10
Figure 4. Pixel Port and Control SDR Output Timing (CP Core)
LLC
P0 TO P19
t
16
t
18
t
15
t
17
05340-006
Figure 5. Pixel Port and Control DDR Output Timing (CP Core)