Datasheet

Data Sheet ADV7181C
Rev. E | Page 17 of 20
PIXEL OUTPUT FORMATTING
Table 10. Pixel Output Formats
Processor, Format,
and Mode
Pixel Port Pins P[19:0]
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDP
Video output
8-bit 4:2:2
YCrCb[7:0]
SDP
Video output
10-bit 4:2:2
YCrCb[9:0]
SDP
Video output
16-bit 4:2:2
Y[7:0] CrCb[7:0]
SDP
Video output
20-bit 4:2:2
Y[9:0] CrCb[7:0]
CP
Video output
12-bit 4:4:4
RGB DDR
D7
1
B[7]↑
R[3]
↓
D6
1
B[6]↑
R[2]
↓
D5
1
B[5]↑
R[1]
↓
D4
1
B[4]↑
R[0]
↓
D3
1
B[3]↑
G[7]
↓
D2
1
B[2]↑
G[6]
↓
D1
1
B[1]↑
G[5]
↓
D0
1
B[0]↑
G[4]
↓
D11
1
G[3]↑
R[7]
↓
D10
1
G[2]↑
R[6]
↓
D9
1
G[1]↑
R[5]
↓
D8
1
G[0]↑
R[4]
↓
CP
Video output
16-bit 4:2:2
CHA[7:0] (for example, Y[7:0]) CHB/C[7:0] (for example, Cr/Cb[7:0])
CP
Video output
20-bit 4:2:2
CHA[9:0] (for example, Y[9:0]) CHB/C[9:0] (for example, Cr/Cb[9:0])
1
↑ indicates data clocked on the rising edge of LLC, ↓ indicates data clocked on the falling edge of LLC.