Datasheet

ADV7174/ADV7179
Rev. B | Page 7 of 52
3.3 V TIMING SPECIFICATIONS
V
AA
= 3.0 V–3.6 V
1
, V
REF
= 1.235 V, R
SET
= 150 Ω. All specifications T
MIN
to T
MAX
2
, unless otherwise noted.
Table 4.
Parameter Conditions
1
Min Typ Max Unit
MPU PORT
3, 4
SCLOCK Frequency 0 400 kHz
SCLOCK High Pulse Width, t
1
0.6 μs
SCLOCK Low Pulse Width, t
2
1.3 μs
Hold Time (Start Condition), t
3
After this period, the first clock is generated 0.6 μs
Setup Time (Start Condition), t
4
Relevant for repeated start condition 0.6 μs
Data Setup Time, t
5
100 ns
SDATA, SCLOCK Rise Time, t
6
300 ns
SDATA, SCLOCK Fall Time, t
7
300 ns
Setup Time (Stop Condition), t
8
0.6 μs
ANALOG OUTPUTS
3, 5
Analog Output Delay 7 ns
DAC Analog Output Skew 0 ns
CLOCK CONTROL AND PIXEL PORT
4, 5
f
CLOCK
27 MHz
Clock High Time, t
9
8 ns
Clock Low Time, t
10
8 ns
Data Setup Time, t
11
3.5 ns
Data Hold Time, t
12
4 ns
Control Setup Time, t
11
4 ns
Control Hold Time, t
12
3 ns
Digital Output Access Time, t
13
12 ns
Digital Output Hold Time, t
14
8 ns
Pipeline Delay, t
PD
6
48 Clock Cycles
TELETEXT
3, 4
Digital Output Access Time, t
16
23 ns
Data Setup Time, t
17
2 ns
Data Hold Time, t
18
6 ns
RESET
CONTROL
, 3 4
RESET
Low Time
6 ns
1
The maximum/minimum specifications are guaranteed over this range. The maximum/minimum values are typical over 3.0 V to 3.6 V range.
2
Temperature range T
MIN
to T
MAX
: –40°C to +85°C.
3
TTL input values are 0 V to 3 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
See Figure 60.