Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- GENERAL DESCRIPTION
- TYPICAL PERFORMANCE CHARACTERISTICS
- FEATURES
- COLOR BAR GENERATION
- SQUARE PIXEL MODE
- COLOR SIGNAL CONTROL
- BURST SIGNAL CONTROL
- NTSC PEDESTAL CONTROL
- PIXEL TIMING DESCRIPTION
- SUBCARRIER RESET
- REAL-TIME CONTROL
- Video Timing Description
- Vertical Blanking Data Insertion
- Mode 0 (CCIR-656): Slave Option
- Mode 0 (CCIR-656): Master Option
- Mode 1: Slave Option HSYNC, BLANK, FIELD
- Mode 1: Master Option HSYNC, BLANK, FIELD
- Mode 2: Slave Option HSYNC, VSYNC, BLANK
- Mode 2: Master Option HSYNC, VSYNC, BLANK
- Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
- POWER-ON RESET
- SCH PHASE MODE
- MPU PORT DESCRIPTION
- REGISTER ACCESSES
- REGISTER PROGRAMMING
- SUBADDRESS REGISTER (SR7–SR0)
- REGISTER SELECT (SR5–SR0)
- MODE REGISTER 1 (MR1)
- MODE REGISTER 2 (MR2)
- MODE REGISTER 3 (MR3)
- MODE REGISTER 4 (MR4)
- TIMING MODE REGISTER 0 (TR0)
- TIMING MODE REGISTER 1 (TR1)
- SUBCARRIER FREQUENCY REGISTERS 3–0
- SUBCARRIER PHASE REGISTER
- CLOSED CAPTIONING EVEN FIELD DATA REGISTERS 1–0
- CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0
- NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0
- TELETEXT REQUEST CONTROL REGISTER (TC07)
- CGMS_WSS REGISTER 0 (C/W0)
- CGMS_WSS REGISTER 1 (C/W1)
- CGMS_WSS REGISTER 2 (C/W2)
- APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS
- APPENDIX 2—CLOSED CAPTIONING
- APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS)
- APPENDIX 4—WIDE SCREEN SIGNALING (WSS)
- APPENDIX 5—TELETEXT
- APPENDIX 6—WAVEFORMS
- APPENDIX 7—OPTIONAL OUTPUT FILTER
- APPENDIX 8—RECOMMENDED REGISTER VALUES
- OUTLINE DIMENSIONS
ADV7174/ADV7179
Rev. B | Page 6 of 52
3.3 V SPECIFICATIONS
V
AA
= 3.0 V–3.6 V
1
, V
REF
= 1.235 V, R
SET
= 150 Ω. All specifications T
MIN
to T
MAX
2
, unless otherwise noted.
Table 3.
Parameter Conditions
1
Min Typ Max Unit
STATIC PERFORMANCE
3
Resolution (Each DAC) 10 Bits
Accuracy (Each DAC)
Integral Nonlinearity R
SET
= 300 Ω ± 0.6 LSB
Differential Nonlinearity Guaranteed Monotonic ± 1 LSB
DIGITAL INPUTS
3
Input High Voltage, V
INH
2 V
Input Low Voltage, V
INL
0.8 V
Input Current, I
IN
3, 4
V
IN
= 0.4 V or 2.4 V ± 1 μA
Input Capacitance, C
IN
10 pF
DIGITAL OUTPUTS
3
Output High Voltage, V
OH
I
SOURCE
= 400 μA 2.4 V
Output Low Voltage, V
OL
I
SINK
= 3.2 mA 0.4 V
Three-State Leakage Current 10 μA
Three-State Output Capacitance 10 pF
ANALOG OUTPUTS
3
Output Current
4, 5
R
SET
= 150 Ω, R
L
= 37.5 Ω 33 34.7 37 mA
Output Current
6
R
SET
= 1041 Ω, R
L
= 262.5 Ω 5 mA
DAC-to-DAC Matching 2.0 %
Output Compliance, V
OC
0 1.4 V
Output Impedance, R
OUT
30 kΩ
Output Capacitance, C
OUT
I
OUT
= 0 mA 30 pF
POWER REQUIREMENTS
3, 7
V
AA
3.0 3.3 3.6 V
Normal Power Mode
I
DAC
(Max)
8
R
SET
= 150 Ω, R
L
= 37.5 Ω 115 120 mA
I
DAC
(Min)
8
R
SET
= 1041 Ω, R
L
= 262.5 Ω 20 mA
I
CCT
9
35 mA
Low Power Mode
I
DAC
(Max)
8
62 mA
I
DAC
(Min)
8
20 mA
I
CCT
9
35 mA
Sleep Mode
I
DAC
10
0.1 μA
I
CCT
11
0.001 μA
Power Supply Rejection Ratio COMP = 0.1 μF 0.01 0.5 %/%
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
2
Temperature range T
MIN
to T
MAX
: –40°C to +85°C.
3
Guaranteed by characterization.
4
Full drive into 37.5 Ω load.
5
DACs can output 35 mA typically at 3.3 V (R
SET
= 150 Ω and R
L
= 37.5 Ω), optimum performance obtained at 18 mA DAC current (R
SET
= 300 Ω and R
L
= 75 Ω).
6
Minimum drive current (used with buffered/scaled output load).
7
Power measurements are taken with clock frequency = 27 MHz. Max T
J
= 110°C.
8
I
DAC
is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces I
DAC
correspondingly.
9
I
CCT
(circuit current) is the continuous current required to drive the device.
10
Total DAC current in sleep mode.
11
Total continuous current during sleep mode.