Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- GENERAL DESCRIPTION
- TYPICAL PERFORMANCE CHARACTERISTICS
- FEATURES
- COLOR BAR GENERATION
- SQUARE PIXEL MODE
- COLOR SIGNAL CONTROL
- BURST SIGNAL CONTROL
- NTSC PEDESTAL CONTROL
- PIXEL TIMING DESCRIPTION
- SUBCARRIER RESET
- REAL-TIME CONTROL
- Video Timing Description
- Vertical Blanking Data Insertion
- Mode 0 (CCIR-656): Slave Option
- Mode 0 (CCIR-656): Master Option
- Mode 1: Slave Option HSYNC, BLANK, FIELD
- Mode 1: Master Option HSYNC, BLANK, FIELD
- Mode 2: Slave Option HSYNC, VSYNC, BLANK
- Mode 2: Master Option HSYNC, VSYNC, BLANK
- Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
- POWER-ON RESET
- SCH PHASE MODE
- MPU PORT DESCRIPTION
- REGISTER ACCESSES
- REGISTER PROGRAMMING
- SUBADDRESS REGISTER (SR7–SR0)
- REGISTER SELECT (SR5–SR0)
- MODE REGISTER 1 (MR1)
- MODE REGISTER 2 (MR2)
- MODE REGISTER 3 (MR3)
- MODE REGISTER 4 (MR4)
- TIMING MODE REGISTER 0 (TR0)
- TIMING MODE REGISTER 1 (TR1)
- SUBCARRIER FREQUENCY REGISTERS 3–0
- SUBCARRIER PHASE REGISTER
- CLOSED CAPTIONING EVEN FIELD DATA REGISTERS 1–0
- CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0
- NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0
- TELETEXT REQUEST CONTROL REGISTER (TC07)
- CGMS_WSS REGISTER 0 (C/W0)
- CGMS_WSS REGISTER 1 (C/W1)
- CGMS_WSS REGISTER 2 (C/W2)
- APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS
- APPENDIX 2—CLOSED CAPTIONING
- APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS)
- APPENDIX 4—WIDE SCREEN SIGNALING (WSS)
- APPENDIX 5—TELETEXT
- APPENDIX 6—WAVEFORMS
- APPENDIX 7—OPTIONAL OUTPUT FILTER
- APPENDIX 8—RECOMMENDED REGISTER VALUES
- OUTLINE DIMENSIONS
ADV7174/ADV7179
Rev. B | Page 38 of 52
CGMS_WSS REGISTER 1 (C/W1)
Bits: C/W17–C/W10
Address : SR4–SR0 = 17H
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52 shows the operations under the control of this register.
C/W17 C/W16 C/W15 C/W14 C/W13 C/W12 C/W11 C/W10
C/W15 – C/W10
CGMS/WSS DATA BITS
C/W17 – C/W16
CGMS DATA BITS
02980-A-051
Figure 52. CGMS_WSS Register 1
Table 19. C/W1 Bit Description
Bit Name Bit No. Description
CGMS/WSS Data Bits C/W15–C/W10
These bit locations are shared by CGMS data and WSS data. In NTSC mode, these bits
are CGMS data. In PAL mode, these bits are WSS data.
CGMS Data Bits C/W17–C/W16 These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 (C/W2)
Bits: C/W27–C/W20
Address: (SR4–SR00) = 18H
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53 shows the operations under the control of this register.
C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20
C/W27 – C/W20
CGMS/WSS DATA BITS
02980-A-052
Figure 53. CGMS_WSS Register 2
Table 20. C/W2 Bit Description
Bit Name Bit No. Description
CGMS/WSS Data Bits C/W27–C/W20
These bit locations are shared by CGMS data and WSS data. In NTSC mode, these
bits are CGMS data. In PAL mode, these bits are WSS data.