Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- GENERAL DESCRIPTION
- TYPICAL PERFORMANCE CHARACTERISTICS
- FEATURES
- COLOR BAR GENERATION
- SQUARE PIXEL MODE
- COLOR SIGNAL CONTROL
- BURST SIGNAL CONTROL
- NTSC PEDESTAL CONTROL
- PIXEL TIMING DESCRIPTION
- SUBCARRIER RESET
- REAL-TIME CONTROL
- Video Timing Description
- Vertical Blanking Data Insertion
- Mode 0 (CCIR-656): Slave Option
- Mode 0 (CCIR-656): Master Option
- Mode 1: Slave Option HSYNC, BLANK, FIELD
- Mode 1: Master Option HSYNC, BLANK, FIELD
- Mode 2: Slave Option HSYNC, VSYNC, BLANK
- Mode 2: Master Option HSYNC, VSYNC, BLANK
- Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
- POWER-ON RESET
- SCH PHASE MODE
- MPU PORT DESCRIPTION
- REGISTER ACCESSES
- REGISTER PROGRAMMING
- SUBADDRESS REGISTER (SR7–SR0)
- REGISTER SELECT (SR5–SR0)
- MODE REGISTER 1 (MR1)
- MODE REGISTER 2 (MR2)
- MODE REGISTER 3 (MR3)
- MODE REGISTER 4 (MR4)
- TIMING MODE REGISTER 0 (TR0)
- TIMING MODE REGISTER 1 (TR1)
- SUBCARRIER FREQUENCY REGISTERS 3–0
- SUBCARRIER PHASE REGISTER
- CLOSED CAPTIONING EVEN FIELD DATA REGISTERS 1–0
- CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0
- NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0
- TELETEXT REQUEST CONTROL REGISTER (TC07)
- CGMS_WSS REGISTER 0 (C/W0)
- CGMS_WSS REGISTER 1 (C/W1)
- CGMS_WSS REGISTER 2 (C/W2)
- APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS
- APPENDIX 2—CLOSED CAPTIONING
- APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS)
- APPENDIX 4—WIDE SCREEN SIGNALING (WSS)
- APPENDIX 5—TELETEXT
- APPENDIX 6—WAVEFORMS
- APPENDIX 7—OPTIONAL OUTPUT FILTER
- APPENDIX 8—RECOMMENDED REGISTER VALUES
- OUTLINE DIMENSIONS
ADV7174/ADV7179
Rev. B | Page 36 of 52
CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0
Bits: CCD15–CCD0
Subaddress: SR4–SR0 = 10H–11H
These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 47 shows how the high and low bytes
are set up in the registers.
BYTE 1
BYTE 0
CCD6 CCD5 CCD3 CCD1CCD4 CCD2 CCD0CCD7
CCD14 CCD13 CCD11 CCD9CCD12 CCD10 CCD8CCD15
002980-A-046
Figure 47. Closed Captioning Data Register
NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0
Bits: PCE15–PCE0, PCO15–PCO0/TXE15–TXE0, TXO15–TXO0
Subaddress: SR4–SR0 = 12H–15H
These 8-bit-wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line-by-line basis in the vertical blanking interval for
both odd and even fields. Figure 48 and Figure 49 show the four control registers. A Logic 1 in any of the bits of these registers has the
effect of turning the pedestal off on the equivalent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of
turning Teletext on the equivalent line when used in PAL.
FIELD 1/3
PCO6 PCO5 PCO3 PCO1PCO4 PCO2 PCO0PCO7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO14 PCO13 PCO11 PCO9PCO12 PCO10 PCO8PCO15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
FIELD 2/4
PCE6 PCE5 PCE3 PCE1PCE4 PCE2 PCE0PCE7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE14 PCE13 PCE11 PCE9PCE12 PCE10 PCE8PCE15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20
LINE 19 LINE 18
FIELD 2/4
02980-A-047
Figure 48. Pedestal Control Registers
FIELD 1/3
FIELD 1/3
FIELD 2/4
FIELD 2/4
TXO6 TXO5 TXO3 TXO1TXO4 TXO2 TXO0TXO7
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXO14 TXO13 TXO11 TXO9TXO12 TXO10 TXO8TXO15
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXE6 TXE5 TXE3 TXE1TXE4 TXE2 TXE0TXE7
TXE14 TXE13 TXE11 TXE9TXE12 TXE10 TXE8TXE15
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
02980-A-048
Figure 49. Teletext Control Registers