Datasheet

ADV7174/ADV7179
Rev. B | Page 33 of 52
TIMING MODE REGISTER 0 (TR0)
Bits: TR07–TR00
Address: SR4–SR0 = 07H
Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
TR01
TR00TR07
TR02TR03TR05TR06 TR04
TIMING
REGISTER RESET
TR07
BLANK INPUT
CONTROL
0 ENABLE
1 DISABLE
TR03
PIXEL PORT
CONTROL
0 8 BIT
1 FORBIDDEN
TR06
MASTER/SLAVE
CONTROL
0 SLAVE TIMING
1 MASTER TIMING
TR00
LUMA DELAY
0 0ns DELAY
0 74ns DELAY
1 148ns DELAY
1
0
1
0
1 222ns DELAY
TR05
TR04
TIMING MODE
SELECTION
0 MODE 0
0 MODE 1
1 MODE 2
1
0
1
0
1 MODE 3
TR02
TR01
02980-A-042
Figure 43. Timing Register 0
Table 15. TR0 Bit Description
Bit Name Bit No. Description
Master/Slave Control TR00 This bit controls whether the ADV7174/ADV7179 is in master or slave mode.
Timing Mode Selection TR02–TR01
These bits control the timing mode of the ADV7174/ADV7179. These modes are
described in more detail in the 3.3 V Timing Specifications table.
BLANK
Input Control
TR03
This bit controls whether the BLANK input is used when the part is in slave mode.
Luma Delay TR05–TR04
These bits control the addition of a luminance delay. Each bit represents a delay of
74 ns.
Pixel Port Control TR06
This bit is used to set the pixel port to accept 8-bit or YCrCb data on Pins P7–P0.
0 must be written here.
Timing Register Reset TR07
Toggling the TR07 from low to high and to low again resets the internal timing
counters. This bit should be toggled after power-up, reset, or changing to a new
timing mode.