Datasheet

ADV7174/ADV7179
Rev. B | Page 23 of 52
Mode 2: Master Option
HSYNC
,
VSYNC
,
BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
and vertical SYNC signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high indicates the start
of an even field. The
BLANK
signal is optional. When the
BLANK
input is disabled, the ADV7174/ADV7179 automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is
illustrated in (NTSC) and (PAL).
illustrates the
Figure 27 Figure 28 Figure 29
HSYNC
,
BLANK
, and
VSYNC
for an even-to-
odd field transition relative to the pixel data.
illustrates the
Figure 30
HSYNC
,
BLANK
, and
VSYNC
for an odd-to-
even field transition relative to the pixel data.
HSYNC
VSYNC
BLANK
PIXEL
DATA
Cb Y Cr Y
PAL = 12 × CLOCK/2
N
T
S
C
=
1
6
×
C
L
O
C
K
/2
PAL = 132
×
CLOCK/2
NTSC = 122
×
CLOCK/2
02980-A-029
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
VSYNC
PIXEL
DATA
Cb Y Cr Y Cb
HSYNC
BLANK
PAL = 12 × CLOCK/2
N
T
S
C
=
1
6
×
C
L
O
C
K
/2
PAL = 132
×
CLOCK/2
NTSC = 122
×
CLOCK/2
PAL = 864
×
CLOCK/2
NTSC = 858
×
CLOCK/2
02980-A-082
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave