Datasheet

ADV7170/ADV7171
Rev. C | Page 7 of 64
TIMING SPECIFICATIONS
V
AA
= 4.75 V to 5.25 V
1
, V
REF
= 1.235 V, R
SET
= 150 Ω. All specifications T
MIN
to T
MAX
2
, unless otherwise noted.
Table 5.
Parameter Conditions Min Typ Max Unit
MPU PORT
3, 4
SCLOCK Frequency 0 400 kHz
SCLOCK High Pulse Width, t
1
0.6 μs
SCLOCK Low Pulse Width, t
2
1.3 μs
Hold Time (Start Condition), t
3
After this period the first clock is generated
Relevant for repeated start condition
0.6 μs
Setup Time (Start Condition), t
4
0.6 μs
Data Setup Time, t
5
100 ns
SDATA, SCLOCK Rise Time, t
6
300 ns
SDATA, SCLOCK Fall Time, t
7
300 ns
Setup Time (Stop Condition), t
8
0.6 μs
ANALOG OUTPUTS
3, 5
Analog Output Delay 7 ns
DAC Analog Output Skew 0 ns
CLOCK CONTROL AND PIXEL PORT
5, 6
f
CLOCK
27 MHz
Clock High Time, t
9
8 ns
Clock Low Time, t
10
8 ns
Data Setup Time, t
11
3.5 ns
Data Hold Time, t
12
4 ns
Control Setup Time, t
11
4 ns
Control Hold Time, t
12
3 ns
Digital Output Access Time, t
13
11 16 ns
Digital Output Hold Time, t
14
4
8 ns
Pipeline Delay, t
15
4
48 Clock cycles
TELETEXT
3, 4, 7
Digital Output Access Time, t
16
20 ns
Data Setup Time, t
17
2 ns
Data Hold Time, t
18
6 ns
RESET CONTROL
3, 4
RESET
Low Time
6 ns
1
The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V range.
2
Ambient temperature range T
MIN
to T
MAX
: −40°C to +85°C. The die temperature, T
J
, must always be kept below 110°C.
3
TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤ 10 pF.
4
Guaranteed by characterization
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel port consists of the following:
Pixel inputs: P15–P0
Pixel controls:
HSYNC
, FIELD/
VSYNC
,
BLANK
Clock input: CLOCK
7
Teletext port consists of the following:
Teletext output: TTXREQ
Teletext input: TTX