Datasheet

ADV7170/ADV7171
Rev. C | Page 39 of 64
75Ω
75Ω
75Ω
75Ω
150Ω
5kΩ 5kΩ
5V (V
CC
) 5V (V
CC
)
100Ω
100Ω
MPU BUS
10, 19, 21,
29, 43
27
DAC D
26
DAC C
31
DAC B
32
DAC A
23
SCLOCK
24
SDATA
34
R
SET
1, 11, 20, 28, 30
V
AA
ADV7170/
ADV7171
25
COMP
33
V
REF
35
SCRESET/RTC
15
HSYNC
16
FIELD/VSYNC
17
BLANK
22
RESET
37
TTX
36
TTXREQ
44
CLOCK
P15–P0
38–42,
2–9, 12–14
18
ALSB GND
5V (V
AA
)5V (V
AA
)
0.1μF0.1μF
UNUSED
INPUTS
SHOULD BE
GROUNDED
10kΩ
5V (V
AA
)
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
100nF
5V (V
AA
)
4kΩ
5V (V
CC
)
100kΩ
100kΩ
RESET
TTX
TTXREQ
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1μF 0.01μF
10μF
5V (V
AA
)
L1
(FERRITE BEAD)
33μF
5V
V
CC
GND
S-VIDEO
00221-054
Figure 54. Recommended Analog Circuit Layout
The circuit in Figure 55 can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the
HSYNC
pulse. This waveform is
guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if a 13.5 MHz
clock is required by the MPEG decoder. This guarantees that the Cr and Cb pixel information is input to the ADV7170/ADV7171 in the
correct sequence.
D
Q
CK
D
Q
CK
CLOC
K
HSYNC
13.5MHz
00221-055
Figure 55. Circuit to Generate 13.5 MHz