Datasheet

ADV7170/ADV7171
Rev. C | Page 37 of 64
TC01 TC00TC07 TC02TC04 TC03TC05TC06
TTXREQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
0 0 0 0 0 PCLK
0 0 0 1 1 PCLK
" " " " " PCLK
1 1 1 0 14 PCLK
1 1 1 1 15 PCLK
TTXREQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0 0 0 0 0 PCLK
0 0 0 1 1 PCLK
" " " " " PCLK
1 1 1 0 14 PCLK
1 1 1 1 15 PCLK
00221-050
Figure 50. Teletext Control Register
C/W07 C/W06 C/W05 C/W04 C/W03 C/W02 C/W01 C/W00
C/W07
WIDE SCREEN
SIGNAL CONTROL
0 DISABLE
1 ENABLE
0 DISABLE
1 ENABLE
C/W05
CGMS ODD FIELD
CONTROL
C/W06
CGMS EVEN FIELD
CONTROL
0 DISABLE
1 ENABLE
C/W04
CGMS CRC CHECK
CONTROL
0 DISABLE
1 ENABLE
C/W03 – C/W00
CGMS DATA BITS
00221-051
Figure 51. CGMS_WSS Register 0
CGMS_WSS REGISTER 1 C/W1 (C/W17 TO C/W10)
(Address [SR4 to SR0] = 17H)
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52
shows the operations under the control of this register.
C/W1 BIT DESCRIPTION
CGMS/WSS Data Bits (C/W15 to C/W10)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode, these bits are CGMS data. In PAL mode, these bits
are WSS data.
CGMS DATA BITS (C/W17 TO C/W16)
These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 C/W1 (C/W27 TO C/W20)
(Address [SR4 to SR0] = 18H)
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53
shows the operations under the control of this register.
C/W2 BIT DESCRIPTION
CGMS/WSS Data Bits (C/W27 to C/W20)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode, these bits are CGMS data. In PAL mode, these bits
are WSS data.
C/W17 C/W16 C/W15 C/W14 C/W13 C/W12 C/W11 C/W10
C/W15 – C/W10
CGMS/WSS DATA BITS
C/W17 – C/W16
CGMS DATA BITS
00221-052
Figure 52. CGMS_WSS Register 1
C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20
C/W27 – C/W20
CGMS/WSS DATA BITS
00221-053
Figure 53. CGMS_ WSS Register 2