Datasheet
ADV7170/ADV7171
Rev. C | Page 35 of 64
TR11 TR10TR17 TR12TR13TR15TR16 TR14
HSYNC TO PIXEL
DATA ADJUST
TR17
TR16
000× T
PCLK
011× T
PCLK
102× T
PCLK
113× T
PCLK
HSYNC TO
FIELD/VSYNC DELAY
TR13
TR12
00
0 × T
PCLK
01
4 × T
PCLK
10
8 × T
PCLK
11
16 × T
PCLK
T
B
HSYNC WIDTH
001× T
PCLK
014× T
PCLK
1016× T
PCLK
1 1 128 × T
PCLK
TR11 TR10
T
A
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
x0T
B
x1T
B
+ 32μs
TR15
TR14
T
C
VSYNC WIDTH
(MODE 2 ONLY)
TR15
TR14
001× T
PCLK
014× T
PCLK
1016× T
PCLK
1 1 128 × T
PCLK
LINE 313 LINE 314LINE 1
T
B
TIMING MODE 1 (MASTER/PAL)
FIELD/VSYNC
T
C
T
A
HSYNC
00221-044
Figure 44. Timing Register 1
SUBCARRIER FREQUENCY REGISTERS 0 TO 3
(FSC3 TO FSC0)
(Address [SR4 to SR00] = 09H to 0CH)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using
the following equation, rounded to the nearest integer:
32
2
27.
.
×
LineVideoOneinCyclesClockMHzofNo
LineVideoofLineOneinValuesFrequencySubcarrierofNo
For example, in NTSC mode,
FhCFdalueVFrequencySubcarrier 107215694085422
1716
5.227
32
==×=
Note that on power-up, F
SC
Register 0 is set to 16h. A value of 1F
as derived above is recommended.
Program as follows:
FSC Register 0: 1FH
FSC Register 2: 7CH
FSC Register 3: F0H
FSC Register 4: 21H
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER
FREQUENCY
REG 3
FSC30 FSC29 FSC27 FSC25FSC28 FSC24FSC31 FSC26
S
UBCARRIE
R
FREQUENCY
REG 2
FSC22 FSC21 FSC19 FSC17FSC20 FSC16FSC23 FSC18
S
UBCARRIE
R
FREQUENCY
REG 1
FSC14 FSC13 FSC11 FSC9FSC12 FSC8FSC15 FSC10
S
UBCARRIE
R
FREQUENCY
REG 0
FSC6 FSC5 FSC3 FSC1FSC4 FSC0FSC7 FSC2
00221-045
Figure 45. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTERS (FP7 TO FP0)
(Address [SR4 to SR0] = 0DH)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°. For normal operation this register is
set to 00Hex.
CLOSED CAPTIONING EVEN FIELD DATA
REGISTER 1 TO 0 (CED15 TO CED0)
(Address [SR4–SR0] = 0E to 0FH)
These 8-bit-wide registers are used to set up the closed
captioning extended data bytes on even fields. Figure 46
shows how the high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CED6 CED5 CED3 CED1CED4 CED2 CED0CED7
CED14 CED13 CED11 CED9CED12 CED10 CED8CED15
00221-046
Figure 46. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD DATA
REGISTERS 1 TO 0 (CCD15 TO CCD0)
(Subaddress [SR4 to SR0] = 10H to 11H)
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 47 shows how the
high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CCD6 CCD5 CCD3 CCD1CCD4 CCD2 CCD0CCD7
CCD14 CCD13 CCD11 CCD9CCD12 CCD10 CCD8CCD15
00221-047
Figure 47. Closed Captioning Data Register