Datasheet

ADV7170/ADV7171
Rev. C | Page 33 of 64
MR41 MR40MR47 MR42MR44 MR43MR45MR46
OUTPUT SELECT
0 YC OUTPUT
1 RGB/YUV OUTPUT
MR40
RGB SYNC
0 DISABLE
1 ENABLE
MR42
PEDESTAL
CONTROL
0 PEDESTAL OFF
1 PEDESTAL ON
MR44
SLEEP MODE
CONTROL
0 DISABLE
1 ENABLE
MR46
ACTIVE VIDEO
FILTER CONTROL
0 DISABLE
1 ENABLE
MR45
MR47
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
VSYNC_3H
0 DISABLE
1 ENABLE
MR43
RGB/YUV
CONTROL
0 RGB OUTPUT
1 YUV OUTPUT
MR41
00221-042
Figure 42. Mode Register 4
MODE REGISTER 4 MR4 (MR47 TO MR40)
(Address (SR4 to SR0) = 04H)
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the
various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
Output Select (MR40)
This bit specifies if the part is in composite video mode or
RGB/YUV mode. Note that in RGB/YUV mode the composite
signal is still available.
RGB/YUV Control (MR41)
This bit enables the output from the RGB DACs to be set to
YUV output video standard.
RGB Sync (MR42)
This bit is used to set up the RGB outputs with the sync
information encoded on all RGB outputs.
VSYNC
_3H (MR43)
When this bit is enabled (1) in slave mode, it is possible to
drive the
VSYNC
active low input for 2.5 lines in PAL mode and
3 lines in NTSC mode. When this bit is enabled in master
mode, the ADV7170/ADV7171 output an active low
VSYNC
signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
Pedestal Control (MR44)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the
ADV7170/ADV7171 are configured in PAL mode.
Active Video Filter Control (MR45)
This bit controls the filter mode applied outside the active video
portion of the line. This filter ensures that the sync rise and fall
times are always on spec regardless of which luma filter is
selected. This mode is enabled by a Logic Level 1.
Sleep Mode Control (MR46)
When this bit is set to 1, sleep mode is enabled. With this mode
enabled, power consumption of the ADV7170/ADV7171 is
reduced to typically 200 nA. The I
2
C registers can be written to
and read from when the ADV7170/ADV7171 are in sleep
mode. If MR46 is set to a 0 when the device is in sleep mode,
the ADV7170/ADV7171 come out of sleep mode and resume
normal operation. Also, if the
RESET
signal is applied during
sleep mode, the ADV7170/ADV7171 come out of sleep mode
and resume normal operation.
Reserved (MR47)
A Logic Level 0 should be written to this bit.
TIMING MODE REGISTER 0 (TR07 TO TR00)
(Address [SR4 to SR0] = 07H)
Figure 43 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.