Datasheet

ADV7170/ADV7171
Rev. C | Page 24 of 64
622 623 624 625 1 2 3 4
5
67
21 22 23
DISPLAY
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
DISPLAY
309 310 311 312 313 314 315 316
317
318 319
334
335 336
DISPLAY
ODD FIELD EVEN FIELD
HSYNC
BLANK
DISPLAY
320
VSYNC
VERTICAL BLANK
VERTICAL BLANK
00221-028
Figure 28. Timing Mode 2 (PAL)
Mode 2: Master Option
HSYNC
,
VSYNC
,
BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high indicates the start of an even field. The
BLANK
signal is optional. When the
BLANK
input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as
per CCIR-624. Mode 2 is shown in (NTSC) and (PAL). shows the Figure 27 Figure 28 Figure 29
HSYNC
,
BLANK
, and
VSYNC
for an
even-to-odd field transition relative to the pixel data. shows the Figure 30
HSYNC
,
BLANK
, and
VSYNC
for an odd-to-even field
transition relative to the pixel data.
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
HSYNC
VSYNC
PIXEL
DATA
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Cb Y Cr
Y
BLANK
00221-029
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
HSYNC
VSYNC
PIXEL
DATA
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
Cb Y Cr Y Cb
BLANK
00221-030
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave