Datasheet

ADV7170/ADV7171
Rev. C | Page 23 of 64
Mode 1: Master Option
HSYNC
,
BLANK
, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7170/ADV7171 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when
HSYNC
is low indicates a new frame, that is, vertical retrace. The
BLANK
signal is optional. When the
BLANK
input is disabled, the
ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following
the timing signal transitions. Mode 1 is shown in (NTSC) and (PAL). illustrates the Figure 24 Figure 25 Figure 26
HSYNC
,
BLANK
, and
FIELD for an odd or even field transition relative to the pixel data.
FIELD
PIXEL
DATA
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Cb Y
Cr Y
HSYNC
BLANK
00221-026
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option
HSYNC
,
VSYNC
,
BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7170/ADV7171 accept horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high indicates the start of an even field. The
BLANK
signal is optional. When the
BLANK
input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as
per CCIR-624. Mode 2 is illustrated in (NTSC) and (PAL). Figure 27 Figure 28
522 523 524 525
1234
5
678
9
10 11
20 21 22
DISPLAY
DISPLAY
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
HSYNC
BLANK
VSYNC
VERTICAL BLANK
00221-027
VERTICAL BLANK
Figure 27. Timing Mode 2 (NTSC)