Datasheet

ADV7170/ADV7171
Rev. C | Page 20 of 64
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7170/ADV7171 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes
in the CCIR656 standard. The H bit is output on the
HSYNC
pin, the V bit is output on the
BLANK
pin, and the F bit is output on the
FIELD/
VSYNC
pin. Mode 0 is illustrated in (NTSC) and (PAL). The H, V, and F transitions relative to the video
waveform are illustrated in .
Figure 21 Figure 22
Figure 23
522 523 524 525 1 2 3 4
5
67
8
9
10 11 20 21 22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELDEVEN FIELD
H
V
F
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
H
V
F
00221-021
Figure 21. Timing Mode 0 (NTSC Master Mode)