Datasheet

ADV7127
–7–REV. 0
3.3 V TIMING SPECIFICATIONS
1
Parameter Min Typ Max Units Condition
ANALOG OUTPUTS
Analog Output Delay, t
6
7.5 ns
Analog Output Rise/Fall Time, t
7
4
1.0 ns
Analog Output Transition Time, t
8
5
15 ns
Analog Output Skew, t
9
6
12 ns
CLOCK CONTROL
f
CLK
7
50 MHz 50 MHz Grade
f
CLK
7
140 MHz 140 MHz Grade
f
CLK
7
240 MHz 240 MHz Grade
Data and Control Setup, t
2
6
1.5 ns
Data and Control Hold, t
2
6
2.5 ns
Clock Pulsewidth High, t
4
1.1 ns f
MAX
= 240 MHz
Clock Pulsewidth Low t
5
6
1.4 ns f
MAX
= 240 MHz
Clock Pulsewidth High t
4
6
2.85 ns f
MAX
= 140 MHz
Clock Pulsewidth Low t
5
6
2.85 ns f
MAX
= 140 MHz
Clock Pulsewidth High t
4
6
8.0 ns f
MAX
= 50 MHz
Clock Pulsewidth Low t
5
6
8.0 ns f
MAX
= 50 MHz
Pipeline Delay, t
PD
6
1.0 1.0 1.0 Clock Cycles
PSAVE Up Time, t
10
6
410 ns
PDOWN Up Time, t
11
8
320 ns
NOTES
1
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) 0 for both 5 V and 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range: T
MIN
to T
MAX
: –40°C to +85°C at 50 MHz and 140 MHz, 0 °C to +70°C at 240 MHz.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization.
8
This power-down feature is only available on the ADV7127 in the TSSOP package.
Specifications subject to change without notice.
CLOCK
DATA
t
4
t
5
t
7
t
8
NOTES:
1. OUTPUT DELAY (t
6
) MEASURED FROM THE 50% POINT OF THE RISING
EDGE OF CLOCK TO THE 50% POINT OF FULL SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t
7
) MEASURED BETWEEN THE 10% AND
90% POINTS OF FULL SCALE TRANSITION.
3. TRANSITION TIME (
t
8
) MEASURED FROM THE 50% POINT OF FULL
SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
t
2
ANALOG OUTPUTS
(I
OUT
, )
DIGITAL INPUTS
(D9–D0)
t
3
t
1
t
6
I
OUT
Figure 1. Timing Diagram
(V
AA
= +3.0 V–3.6 V
2
, V
REF
= 1.235 V, R
SET
= 560 V. All specifications T
MIN
to T
MAX
3
unless
otherwise noted, T
J MAX
= 1108C)