Datasheet

ADV3226/ADV3227
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS (SERIAL)
Table 2.
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t
1
10 ns
CLK Pulse Width t
2
10 ns
Serial Data Hold Time t
3
10 ns
CLK Pulse Separation, Serial Mode t
4
10 ns
CLK to
UPDATE
Delay
t
5
10 ns
UPDATE
Pulse Width
t
6
10 ns
CLK to DATAOUT Valid, Serial Mode t
7
50 ns
Propagation Delay,
UPDATE
to Switch On or Off
20 ns
Data Load Time, CLK = 5 MHz, Serial Mode 1.6 μs
CLK,
UPDATE
Rise and Fall Times
50 ns
RESET
Time
30 ns
Timing Diagram—Serial Mode
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t
2
t
4
1
0
1
0
DATAIN
CLK
1 = LATCHED
t
1
t
3
0
= TRANSPAREN
T
DATAOUT
OUT07 (D4) OUT07 (D3) OUT00 (D0)
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
7
t
6
t
5
UPDATE
08653-002
Figure 2. Timing Diagram, Serial Mode
LOGIC LEVELS
Table 3. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
IH
I
IL
I
OH
I
OL
RESET
,
SER
/PAR,
CLK, DATAIN,
CE
,
UPDATE
RESET
,
SER
/PAR,
CLK, DATAIN,
CE
,
UPDATE
DATAOUT DATAOUT
SER
/PAR,
CLK, DATAIN,
CE
,
UPDATE
SER
/PAR, CLK,
DATAIN,
CE
,
UPDATE
RESET
RESET
DATAOUT DATAOUT
2.0 V min 0.8 V max 2.4 V min 0.4 V max 2 μA max 2 μA max 2 μA max 300 μA max 3 mA min 1 mA min