Datasheet
ADV3226/ADV3227
Rev. 0 | Page 10 of 24
TRUTH TABLE AND LOGIC DIAGRAM
Table 8. Operation Truth Table
1
CE
UPDATE
CLK DATAIN DATAOUT
RESET
SER
/PAR
Description
1 X X X X X X No change in logic.
0 X
Data
I
2
Data
I-80
X 0 The data on the serial DATAIN line is loaded into the serial register.
The first bit clocked into the serial register appears at DATAOUT 80
clock cycles later.
0 X 0 D0…D4 N/A
3
in
parallel
mode
4
X 1 The data on the parallel data lines, D0 to D4, are loaded into the
80-bit serial shift register location addressed at A0 to A3.
0 0 X X X 1 X
Data in the 80-bit shift register transfers into the parallel latches
that control the switch array. Latches are transparent.
X X X X X 0 X Asynchronous operation. All outputs are disabled. Second rank
latches are cleared. Remainder of logic is unchanged.
1
X is don’t care.
2
Data
I
: serial data.
3
N/A means not applicable.
4
DATAOUT remains active in parallel mode and always reflects the state of the MSB of the serial shift register.
D
CLK
Q
4 TO 16 DECODER
A0
A1
A2
CLK
16
256
DATA IN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
CE
UPDATE
OUT0 EN
DATA
OUT
PARALLEL
DATA
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D1
D2
D3
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
D
LE
QCLR
OUT15
EN
OUTPUT ENABLESWITCH MATRIX
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
D
Q
CLK
D4
S
D1
Q
D0
DECODE
D
LE
QCLR
OUT0
EN
D
LE
OUT0
B0
Q
D
LE
Q
OUT0
B1
D
LE
Q
OUT0
B2
D
LE
Q
OUT0
B3
D
LE
OUT1
B0
Q
D
LE
QCLR
OUT14
EN
D
LE
OUT15
B0
Q
D
LE
OUT15
B1
Q
D
LE
OUT15
B2
Q
D
Q
CLK
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
D
LE
OUT15
B3
Q
OUT8 EN
OUT9 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
A3
OUTPUT
ADDRESS
RESET
(OUTPUT ENABLE)
08653-006
Figure 6. Logic Diagram