Datasheet

ADV3221/ADV3222
Rev. 0 | Page 17 of 20
THEORY OF OPERATION
The ADV3221/ADV3222 are dual-supply, high performance
4:1 analog multiplexers, optimized for switching between
multiple video sources. High peak slew rates enable wide
bandwidth operation for large input signals. Internal com-
pensation provides for high phase margin, allowing low
overshoot and fast settling for pulsed inputs. Low enabled
and disabled power consumption make the ADV3221 and
ADV3222 ideal for constructing larger arrays.
The ADV3221/ADV3222 are organized as four input transcon-
ductance stages tied in parallel with a single output transimpedance
stage followed by a unity-gain buffer. Internal voltage feedback
sets the gain. The ADV3221 is configured as a gain of 1, while
the ADV3222 uses a resistive feedback network and ground buffer
to realize gain-of-two operation (see Figure 60).
V
+
V–
IN0
V+
V–
IN1
V+
V–
GND
×1
(2 MORE INPUTS)
1kΩ
1kΩ
OUT
08652-060
Figure 60. Conceptual Diagram of ADV3222
When not in use, the output can be placed in a low power, high
impedance disabled mode via the
CS
logic input. This is useful
when paralleling multiple ADV3221/ADV3222 devices in a
system to create larger switching arrays.
Switching between the inputs is controlled with the A0, A1, and
CS
logic inputs, which are latched through two stages of asyn-
chronous latches.
CK1
controls the first stage latch, and
CK2
controls the second stage latch. The latch state is dependent on
the level of the
CK1
and
CK2
signals, and it is not edge triggered.
When using multiple ADV3221/ADV3222 devices in a switch
design, this double buffered logic allows the use of the
CK2
signal
to simultaneously update all ADV3221/ADV3222 devices in a
system. The A0 and A1 logic inputs select which input is connected
to the output (A1 is the most significant bit, A0 is the least signifi-
cant bit), and the
CS
logic input determines whether the output
is enabled or disabled.