Datasheet

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800 MHz, 4:1 Analog Multiplexer

ADV3221/ADV3222

Rev. 0

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FEATURES

Excellent ac performance

−3 dB bandwidth

800 MHz (200 mV p-p)

750 MHz (2 V p-p)

Slew rate: 2400 V/μs

Low power: 75 mW, V

= ±5 V

Excellent video performance

100 MHz, 0.1 dB gain flatness

0.02% differential gain error/0.02° differential phase error

= 150 Ω)

ADV3221 is a pin-for-pin upgrade to the HA4344

Gain = +1 (ADV3221) or gain = +2 (ADV3222)

Low all hostile crosstalk of −85 dB @ 5 MHz, and

−58 dB @ 100 MHz

Latched control lines for synchronous switching

High impedance output disable allows connection of

multiple devices without loading the output bus

16-lead SOIC

APPLICATIONS

Routing of high speed signals including

Video (NTSC, PAL, S, SECAM, YUV, RGB)

Compressed video (MPEG, wavelet)

3-level digital video (HDB3)

Data communications

Telecommunications

FUNCTIONAL BLOCK DIAGRAM

LATCH

DECODE

100kΩ 100kΩ

IN0

IN1

IN2

IN3

G = +1

(G = +2)

OUT

ENABLE

08652-001

Figure 1.

GENERAL DESCRIPTION

The ADV3221 and ADV3222 are high speed, high slew rate,

buffered 4:1 analog multiplexers. They offer a −3 dB signal

bandwidth greater than 800 MHz and channel switch times

of less than 20 ns with 1% settling. With lower than −58 dB of

crosstalk and −67 dB isolation (at 100 MHz), the ADV3221 and

ADV3222 are useful in many high speed applications. The diffe-

rential gain error of less than 0.02% and differential phase error

of less than 0.02°, together with 0.1 dB gain flatness out to 100 MHz

while driving a 75 Ω back terminated load, make the ADV3221

and ADV3222 ideal for all types of signal switching.

The ADV3221/ADV3222 include an output buffer that can be

placed into a high impedance state. This allows multiple outputs

to be connected together for cascading stages without the off

channels loading the output bus. The ADV3221 has a gain of

+1, and the ADV3222 has a gain of +2; they both operate on ±5 V

supplies while consuming less than 7.5 mA of idle current. The

channel switching is performed via latched control lines, allowing

synchronous updating in a multiple ADV3221/ADV3222 envi-

ronment.

The ADV3221/ADV3222 are offered in a 16-lead SOIC package

and are available over the extended industrial temperature range of

−40°C to +85°C.

Summary of content (20 pages)

PAGE 1
800 MHz, 4:1 Analog Multiplexer ADV3221/ADV3222 CS A0 A1 D Q D LATCH D D Q Q LATCH LATCH D D Q LATCH ENABLE Q LATCH IN0 IN1 IN2 IN3 G = +1 (G = +2) OUT Q LATCH CK1 CK2 100kΩ 08652-001 Excellent ac performance −3 dB bandwidth 800 MHz (200 mV p-p) 750 MHz (2 V p-p) Slew rate: 2400 V/μs Low power: 75 mW, VS = ±5 V Excellent video performance 100 MHz, 0.1 dB gain flatness 0.02% differential gain error/0.
PAGE 2
ADV3221/ADV3222 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Circuit Diagrams ............................................................................ 16 Functional Block Diagram ...........................................................
PAGE 3
ADV3221/ADV3222 SPECIFICATIONS VS = ±5 V, TA = 25°C, RL = 150 Ω, CL = 2 pF, ADV3221 at G = +1, ADV3222 at G = +2, unless otherwise noted. Table 1.
PAGE 4
ADV3221/ADV3222 Parameter POWER SUPPLIES Supply Current Test Conditions/Comments Supply Voltage Range Power Supply Rejection (PSR) Min ADV3221 Typ Max ADV3222 Typ Max Unit V+, output enabled, no load V+, output disabled (CS high) 7 1.6 8 2.0 7.5 1.8 9 2.2 mA mA V−, output enabled, no load V−, output disabled (CS high) 7 1.6 8 2.0 7.5 1.8 9 2.2 mA mA ±5.5 V dB dB +85 °C °C/W ±4.
PAGE 5
ADV3221/ADV3222 Timing and Programming Diagrams t1 t2 1 t3 CK1 0 t4 1 CK2 0 t5 08652-002 1 A0, A1, CS 0 Figure 2. Timing Diagram CK1 CK2 A0 A1 OUTPUT XX IN0 IN1 Figure 3. Programming Example Rev.
PAGE 6
ADV3221/ADV3222 ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION Table 4. Rating 12 V V− to V+ 0 V to V+ (V+ − 1 V) to (V− + 1 V) Momentary 50 mA −65°C to +150°C −40°C to +85°C 300°C 150°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5.
PAGE 7
ADV3221/ADV3222 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN0 1 16 V+ GND 2 15 A0 14 A1 IN1 3 CS TOP VIEW IN2 5 (Not to Scale) 12 OUT 11 CK2 GND 6 13 IN3 7 10 CK1 GND 8 9 V– 08652-005 GND 4 ADV3221/ ADV3222 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No.
PAGE 8
ADV3221/ADV3222 0pF 2pF 4.7pF 10pF 1 10 100 1k 10k FREQUENCY (MHz) 10 100 1k 10k FREQUENCY (MHz) Figure 7. ADV3221 Large Signal Response vs. Capacitive Load, 2 V p-p 0.2 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 1k 10k 0pF 2pF 4.7pF 10pF 1 10 100 1k 10k FREQUENCY (MHz) Figure 10. ADV3222 Large Signal Response vs. Capacitive Load, 2 V p-p 0.2 0pF 2pF 4.7pF 10pF 0pF 2pF 4.7pF 10pF 0.1 VOUT (V) 0.1 0 –0.1 0 –0.1 0 5 10 TIME (ns) 15 20 –0.2 08652-014 –0.
PAGE 9
ADV3221/ADV3222 2 2 0pF 2pF 4.7pF 10pF 1 VOUT (V) 0 0 –1 –1 0 5 10 15 20 TIME (ns) –2 08652-018 –2 0 1.5 2000 1.0 10 15 20 TIME (ns) Figure 12. ADV3221 Large Signal Pulse Response vs. Capacitive Load, 2 V p-p 3000 5 08652-021 VOUT (V) 1 0pF 2pF 4.7pF 10pF Figure 15. ADV3222 Large Signal Pulse Response vs. Capacitive Load, 2 V p-p 1.5 4000 3000 1.0 0.5 dv/dt 0 0 –1000 –0.5 0.
PAGE 10
ADV3221/ADV3222 1.5 1.5 2.1 VOUT FALLING EDGE 1.0 1.9 1.0 2.1 VOUT FALLING EDGE 1.9 1.7 1.7 1.3 A0 VOUT (V) 1.5 A0 0 –0.5 1.5 0 1.3 A0 (V) 0.5 A0 (V) –0.5 1.1 1.1 VOUT RISING EDGE –1.0 –1.0 0.9 0.7 0 10 20 30 TIME (ns) 0.9 –1.5 08652-024 –1.5 VOUT RISING EDGE 0.7 0 10 20 08652-027 VOUT (V) 0.5 30 TIME (ns) Figure 18. ADV3221 Switching Time Figure 21.
PAGE 11
ADV3221/ADV3222 1.5 1.9 1.0 2.1 1.5 2.1 1.9 1.0 INPUT +1V INPUT +0.5V 1.7 1.7 VOUT (V) 1.3 CS (V) 1.3 –0.5 1.1 INPUT –1V –1.0 –1.0 0.9 0.7 0 10 20 30 40 TIME (ns) 0.9 0.7 –1.5 08652-030 –1.5 1.1 INPUT –0.5V 0 10 20 30 40 TIME (ns) Figure 24. ADV3221 Disable Timing Figure 27.
PAGE 12
ADV3221/ADV3222 1.25 5 1.25 5 OUTPUT 4 0.75 3 2 0.50 2 ERROR 0 0 –0.25 ERROR (%) 0.25 1 1.00 0.75 INPUT 0.50 0.25 1 ERROR 0 0 –1 –0.25 –2 –0.50 –2 –0.50 –3 –0.75 –3 –0.75 –4 –1.00 –4 –1.00 –5 –1.25 –5 –1 OUTPUT (V) 1.00 3 OUTPUT (V) 4 3 4 5 6 7 8 9 10 TIME (ns) –1.25 0 1 0 0 –10 –10 –20 –20 PSR (dB) –30 PSR (V–) –40 PSR (V+) –50 –80 10k FREQUENCY (MHz) –90 0.1 1 10 100 1k 10k 10M 100M Figure 34.
PAGE 13
ADV3221/ADV3222 –20 –20 –30 –30 –40 –50 CROSSTALK (dB) –60 –70 –80 –50 –60 –70 –80 –90 10 100 1k 10k FREQUENCY (MHz) –100 1 –30 –40 –40 –50 –50 CROSSTALK (dB) –30 –60 –70 –80 –70 –80 –90 –100 –100 –110 1k 10k FREQUENCY (MHz) –110 1 10 100 1k 10k FREQUENCY (MHz) Figure 37. ADV3221 Crosstalk, Adjacent Channel Figure 40.
PAGE 14
ADV3221/ADV3222 1M 0 100k –10 –15 INPUT S11 (dB) INPUT IMPEDANCE (Ω) –5 10k 1k –20 –25 –30 –35 100 –40 10 100 –50 0.1 08652-048 1 1k FREQUENCY (MHz) 1k 10k 100k 10k 1k 100 10 1 0.1 1 10 100 1k FREQUENCY (MHz) 100k 10k 1k 100 10 1 0.1 1 10 100 08652-052 DISABLED OUTPUT IMPEDANCE (Ω) 1M 08652-049 1k FREQUENCY (MHz) Figure 43. ADV3221 Disabled Output Impedance Figure 46.
PAGE 15
ADV3221/ADV3222 5 5 5 2.5 4 2.0 3 3 1.5 1 1 0 0 –1 –1 –2 –2 –3 –4 120 140 160 180 1 0.5 0 0 –1 –0.5 –2 –1.0 –3 –3 –1.5 –4 –4 –2.0 –5 200 –5 TIME (ns) 0 20 60 80 –2.5 100 Figure 51. ADV3222 Overdrive Recovery 0 70 SECOND-ORDER INTERCEPT (dBm) –10 HD3 10dBm HARMONIC DISTORTION (dBc) 40 TIME (ns) Figure 48.
PAGE 16
ADV3221/ADV3222 CIRCUIT DIAGRAMS V+ OUT 2.8pF (ADV3221) 3.0pF (ADV3222) 08652-006 V– 08652-009 IN 1.8pF Figure 57. ADV3221/ADV3222 Disabled Output Figure 54. ADV3221/ADV3222 Analog Input V+ 08652-007 100kΩ (CK1, CK2 ONLY) V– GND 08652-010 1kΩ A0, A1, CS CK1, CK2 OUT Figure 58. ADV3221/ADV3222 Logic Input Figure 55. ADV3221 Enabled Analog Output V+ OUT GND 08652-008 1kΩ A0, A1, CK1, CK2, CS IN, OUT V– GND 08652-011 1kΩ Figure 59. ADV3221/ADV3222 ESD Schematic Figure 56.
PAGE 17
ADV3221/ADV3222 THEORY OF OPERATION The ADV3221/ADV3222 are dual-supply, high performance 4:1 analog multiplexers, optimized for switching between multiple video sources. High peak slew rates enable wide bandwidth operation for large input signals. Internal compensation provides for high phase margin, allowing low overshoot and fast settling for pulsed inputs. Low enabled and disabled power consumption make the ADV3221 and ADV3222 ideal for constructing larger arrays.
PAGE 18
ADV3221/ADV3222 APPLICATIONS INFORMATION The ADV3221 and ADV3222 are high speed multiplexers used to switch video or RF signals. The low output impedance of the ADV3221/ADV3222 allows the output environment to be optimized for use in 75 Ω or 50 Ω systems by choosing the appropriate series termination resistor. For composite video applications, the ADV3222 (gain of +2) is typically used to provide compensation for the loss of the output termination.
PAGE 19
ADV3221/ADV3222 OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.