Datasheet

ADV3200/ADV3201
Rev. 0 | Page 27 of 36
THEORY OF OPERATION
The ADV3200/ADV3201 are single-ended crosspoint arrays
with 32 outputs, each of which can be connected to any one
of 32 inputs. Thirty-two switchable input stages are connected
to each output buffer to form 32-to-1 multiplexers. There are 32
of these multiplexers, each with its inputs wired in parallel, for a
total array of 1024 stages forming a multicast-capable crosspoint
switch (see Figure 97).
In addition to connecting to any of the nominal inputs (INxx),
each output can also be connected to an associated OSDxx input
through an additional 2-to-1 multiplexer at each output. This
2-to-1 multiplexer switches between the output of the 32-to-1
multiplexer and the OSDxx input.
x1
OUT00
VPOS
VNEG
FROM INPUT
STAGES
VPOS
VNEG
OSD00
OSDS00
07176-006
Figure 95. Conceptual Diagram of Single Output Channel, G = +1 (ADV3200)
Decoding logic for each output selects one (or none) of the
input stages to drive the output stage. The enabled input stage
drives the output stage, which is configured as a unity-gain
amplifier in the ADV3200 (see Figure 95).
In the ADV3201, an internal resistive feedback network and
reference buffer provide for a total output stage gain of +2 (see
Figure 96). The input voltage to the reference buffer is the
VREF pin. This voltage is common to the entire chip and needs
to be driven from a low impedance source to avoid crosstalk.
OUT00
x1
VPOS
VNEG
FROM INPUT
STAGES
VPOS
VNEG
VREF
VPOS
VNEG
OSD00
OSDS00
2kΩ
2kΩ
07176-007
Figure 96. Conceptual Diagram of Single Output Channel, G = +2 (ADV3201)
Each input to the ADV3200/ADV3201 is buffered by a receiver.
This receiver provides overvoltage protection for the input
stages by limiting signal swing. In the ADV3200, the output
of the receiver is limited to ±1.2 V about VREF, whereas in the
ADV3201, the signal swing is limited to ±1.2 V about midsupply.
This receiver is configured as a voltage feedback unity-gain
amplifier. Excess loop gain bandwidth product reduces the
effect of the closed-loop gain on the bandwidth of the device.
SWITCH
MATRIX
SYNC-TIP
CLAMP
RECEIVER
INxx
GND
GND
OPTIONAL
AC COUPLING
CAPACITOR
75Ω
OUTxx
75Ω
75Ω
ADV3200/ADV3201
VREFOSDxx OSDSxxVCLAMP
BYPASS SYNC-TIP
CLAMP
07176-110
OUTPUT
BUFFER
G = +1 (ADV3200)
G = +2 (ADV3201)
Figure 97. ADV3200/ADV3201 Signal Chain (Single I/O Path)